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| ? 2010 microchip technology inc. ds70139g dspic30f2011/2012/3012/3013 data sheet high-performance, 16-bit digital signal controllers
ds70139g-page 2 ? 2010 microchip technology inc. information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, mi wi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-631-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semico nductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection featur e may be a violation of the digi tal millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2010 microchip technology inc. ds70139g-page 3 dspic30f2011/2012/3012/3013 high-performance modified risc cpu: ? modified harvard architecture ? c compiler optimized instruction set architecture ? flexible addressing modes ? 83 base instructions ? 24-bit wide instructions, 16-bit wide data path ? up to 24 kbytes on-chip flash program space ? up to 2 kbytes of on-chip data ram ? up to 1 kbytes of nonvolatile data eeprom ? 16 x 16-bit working register array ? up to 30 mips operation: - dc to 40 mhz external clock input - 4 mhz - 10 mhz oscillator input with pll active (4x, 8x, 16x) ? up to 21 interrupt sources: - 8 user-selectable priority levels - 3 external interrupt sources - 4 processor trap sources dsp features: ? dual data fetch ? modulo and bit-reversed modes ? two 40-bit wide accumulators with optional saturation logic ? 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier ? all dsp instructions are single cycle - multiply-accumulate (mac) operation ? single-cycle 16 shift peripheral features: ? high-current sink/source i/o pins: 25 ma/25 ma ? three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules ? 16-bit capture input functions ? 16-bit compare/pwm output functions ? 3-wire spi modules (supports four frame modes) ?i 2 c? module supports multi-master/slave mode and 7-bit/10-bit addressing ? up to two addressable uart modules with fifo buffers analog features: ? 12-bit analog-to-digital converter (adc) with: - 200 ksps conversion rate - up to 10 input channels - conversion available during sleep and idle ? programmable low-voltage detection (plvd) ? programmable brown-out reset special microcontroller features: ? enhanced flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100k (typical) ? data eeprom memory: - 100,000 erase/write cycle (min.) for industrial temperature range, 1m (typical) ? self-reprogrammable under software control ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? flexible watchdog timer (wdt) with on-chip low-power rc oscillator for reliable operation ? fail-safe clock monitor operation: - detects clock failure and switches to on-chip low-power rc oscillator ? programmable code protection ? in-circuit serial programming? (icsp?) ? selectable power management modes: - sleep, idle and alternate clock modes cmos technology: ? low-power, high-speed flash technology ? wide operating voltage range (2.5v to 5.5v) ? industrial and extended temperature ranges ? low-power consumption note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). high-performance, 16-bit digital signal controllers dspic30f2011/2012/3012/3013 ds70139g-page 4 ? 2010 microchip technology inc. dspic30f2011/2012/3012/3013 sensor family pin diagrams device pins program memory sram bytes eeprom bytes timer 16-bit input cap output comp/std pwm a/d 12-bit 200 ksps uart spi i 2 c ? bytes instructions dspic30f2011 18 12k 4k 1024 ? 3 2 2 8 ch 1 1 1 dspic30f3012 18 24k 8k 2048 1024 3 2 2 8 ch 1 1 1 dspic30f2012 28 12k 4k 1024 ? 3 2 2 10 ch 1 1 1 dspic30f3013 28 24k 8k 2048 1024 3 2 2 10 ch 2 1 1 emud1/sosci/t2ck/ u1atx/cn1/rc13 emuc1/sosco/t1ck/u1arx/cn0/rc14 osc1/clki v dd osc2/clko/rc15 pgd/emud/an4/u1tx/sdo1/scl/cn6/rb4 av dd pgc/emuc/an5/u1rx /sdi1/sda/cn7/rb5 emud2/an7/oc2/ic2/int2/rb7 emud3/an0/v ref +/cn2/rb0 v ss an6/sck1/int0/ocfa/rb6 av ss emuc3/an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 emuc2/oc1/ic1/int1/rd0 18-pin pdip and soic dspic30f2011 dspic30f3012 an3/cn5/rb3 mclr 28-pin pdip and soic mclr v ss v dd emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 av dd av ss an2/ss1 /lvdin/cn4/rb2 ic2/int2/rd9 emuc2/ic1/int1/rd8 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/ u1atx/cn1/rc13 v ss osc2/clko/rc15 osc1/clki v dd sck1/int0/rf6 pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/s do1/scl/rf3 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an6/ocfa/rb6 emud2/an7/rb7 an8/oc1/rb8 an9/oc2/rb9 cn17/rf4 cn18/rf5 dspic30f2012 mclr v ss v dd emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 av dd av ss an2/ss1 /lvdin/cn4/rb2 ic2/int2/rd9 emuc2/ic1/int1/rd8 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/ u1atx/cn1/rc13 v ss osc2/clko/rc15 osc1/clki v dd sck1/int0/rf6 pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an6/ocfa/rb6 emud2/an7/rb7 an8/oc1/rb8 an9/oc2/rb9 u2rx/cn17/rf4 u2tx/cn18/rf5 dspic30f3013 28-pin spdip and soic ? 2010 microchip technology inc. ds70139g-page 5 dspic30f2011/2012/3012/3013 pin diagrams 28-pin qfn-s (1) emuc3/an1/v ref -/cn3/rb1 emud3/an0/v ref +/cn2/rb0 mclr 28 27 26 25 24 23 22 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 dspic30f2011 nc nc nc nc nc nc nc nc av dd av ss an6/sck1/int0/ocfa/rb6 emud2/an7/oc2/ic2/int2/rb7 v dd v ss pgc/emuc/an5/u1rx/s di1/sda/cn7/rb5 an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 v ss osc1/clki osc2/clko/rc15 pgd/emud/an4/u1tx/sdo1/scl/cn6/rb4 emuc2/oc1/ic1/int1/rd0 emud1/sosc1/t2ck/u1atx/cn1/rc13 emuc1/sosco/t1ck/u1arx/cn0/rc14 v dd note 1: the metal plane at the bottom of the dev ice is not connected to any pins and is recommended to be connected to v ss externally. dspic30f2011/2012/3012/3013 ds70139g-page 6 ? 2010 microchip technology inc. pin diagrams 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic30f2012 emud1/sosci/t2ck/ u1atx/cn1/rc13 5 4 av dd av ss an6/ocfa/rb6 emud2/an7/rb7 an8/oc1/rb8 an9/oc2/rb9 cn17/rf4 cn18/rf5 v dd v ss pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 sck1/int0/rf6 emuc2/ic1/int1/rd8 mclr emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 an4/cn6/rb4 an5/cn7/rb5 v ss osc1/clki osc2/clko/rc15 emuc1/sosco/t1ck/u1arx/cn0/rc14 v dd ic2/int2/rd9 28-pin qfn-s (1) note 1: the metal plane at the bottom of the dev ice is not connected to any pins and is recommended to be connected to v ss externally. ? 2010 microchip technology inc. ds70139g-page 7 dspic30f2011/2012/3012/3013 pin diagram 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 nc nc nc nc nc nc v dd nc v ss pgc/emuc/an5/u1rx/sdi1/sda/cn7/rb5 nc nc emuc3 / an1/v ref -/cn3/rb1 emud3 / an0/v ref +/cn2/rb0 mclr av dd nc an6/sck1/int0/ocfa/rb6 emud2 / an7/oc2/ic2/int2/rb7 an2/ss1 /lvdin/cn4/rb2 nc an3/cn5/rb3 nc nc nc v ss osc1/clki osc2/clko/rc15 pgd/emud / an4/u1tx/sdo1/scl/cn6/rb4 nc emuc2 / oc1/ic1/int1/rd0 nc nc emuc1/sosco/t1ck/u1arx/cn0/rc14 nc nc v dd 6 22 33 34 nc av ss nc nc emud1 / sosci/t2ck/u1atx/cn1/rc13 v ss nc dspic30f3012 44-pin qfn (1) note 1: the metal plane at the bottom of the dev ice is not connected to any pins and is recommended to be connected to v ss externally. dspic30f2011/2012/3012/3013 ds70139g-page 8 ? 2010 microchip technology inc. pin diagrams 44-pin qfn (1) an8/oc1/rb8 an9/oc2/rb9 u2rx/cn17/rf4 nc u2tx/cn18/rf5 nc v dd nc v ss pgc/emuc/u1rx/sdi1/sda/rf2 nc nc emuc3 / an1/v ref -/cn3/rb1 emud3 / an0/v ref +/cn2/rb0 mclr av dd nc an6/ocfa/rb6 emud2/an7/rb7 an2/ss1 /lvdin/cn4/rb2 nc an3/cn5/rb3 an4/cn6/rb4 an5/cn7/rb5 nc v ss osc1/clki osc2/clko/rc15 pgd/emud/u1tx/sdo1/scl/rf3 sck1/int0/rf6 emuc2/ic1/int1/rd8 nc nc emuc1/sosco/t1ck/u1arx/cn0/rc14 nc ic2/int2/rd9 v dd nc av ss nc nc emud1/sosci/t2ck/u1atx/cn1/rc13 v ss nc dspic30f3013 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34 note 1: the metal plane at the bottom of the dev ice is not connected to any pins and is recommended to be connected to v ss externally. ? 2010 microchip technology inc. ds70139g-page 9 dspic30f2011/2012/3012/3013 table of contents 1.0 device overview ............................................................................................................. ........................................................... 11 2.0 cpu architecture overview................................................................................................... ..................................................... 19 3.0 memory organization ......................................................................................................... ........................................................ 29 4.0 address generator units..................................................................................................... ....................................................... 43 5.0 flash program memory........................................................................................................ ...................................................... 49 6.0 data eeprom memory .......................................................................................................... ................................................... 55 7.0 i/o ports ................................................................................................................... .................................................................. 59 8.0 interrupts .................................................................................................................. .................................................................. 65 9.0 timer1 module ............................................................................................................... ............................................................ 73 10.0 timer2/3 module ............................................................................................................ ............................................................ 77 11.0 input capture module....................................................................................................... .......................................................... 83 12.0 output compare module ...................................................................................................... ...................................................... 87 13.0 spi? module ................................................................................................................ ............................................................. 93 14.0 i2c? module ................................................................................................................ ............................................................. 97 15.0 universal asynchronous receiver transmitter (uart) module .................................................................. ............................ 105 16.0 12-bit analog-to-digital converter (adc) module ............................................................................ ........................................ 113 17.0 system integration ......................................................................................................... .......................................................... 123 18.0 instruction set summary .................................................................................................... ...................................................... 137 19.0 development support........................................................................................................ ....................................................... 145 20.0 electrical characteristics ................................................................................................. ......................................................... 149 21.0 packaging information...................................................................................................... ........................................................ 187 index .......................................................................................................................... ........................................................................ 201 the microchip web site ......................................................................................................... ............................................................ 207 customer change notification service ........................................................................................... ................................................... 207 customer support ............................................................................................................... ............................................................... 207 reader response ................................................................................................................ .............................................................. 208 product identification system .................................................................................................. .......................................................... 209 to our valued customers it is our intention to provide our valued cu stomers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicati ons to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/docum entation issues become known to us, we will publish an errata sheet. t he errata will s pecify the revisi on of silicon and revision of doc ument to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. dspic30f2011/2012/3012/3013 ds70139g-page 10 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 11 dspic30f2011/2012/3012/3013 1.0 device overview this data sheet contains information specific to the dspic30f2011, dspic30f20 12, dspic30f3012 and dspic30f3013 digital signal controllers (dsc). these devices contain extensive digital signal processor (dsp) functionality within a high-performance 16-bit microcontroller (mcu) architecture. the following block diagrams depict the architecture for these devices: ? figure 1-1 illustrates the dspic30f2011 ? figure 1-2 illustrates the dspic30f2012 ? figure 1-3 illustrates the dspic30f3012 ? figure 1-4 illustrates the dspic30f3013 following the block diagrams, table 1-1 relates the i/o functions to pinout information. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). dspic30f2011/2012/3012/3013 ds70139g-page 12 ? 2010 microchip technology inc. figure 1-1: dspic30f20 11 block diagram power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode & control osc1/clki mclr v dd , v ss pgd/emud/an4/u1tx/sdo1/scl/cn6/rb4 low-voltage detect uart1 timing generation pgc/emuc/an5/u1rx/sdi1/sda/cn7/r b5 16 pch pcl program counter alu<16> 16 24 24 24 24 x data bus ir i 2 c? an6/sck1/int0/ocfa/rb6 emud2/an7/oc2/ic2/int2/rb7 pcu 12-bit adc timers input capture module output compare module emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 portb portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 osc2/clko/rc15 av dd , av ss 16 16 16 16 16 portc 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (512 bytes) ram x data (512 bytes) ram address latch address latch emuc2/oc1/ic1/int1/rd0 16 spi1 address latch program memory (12 kbytes) data latch 16 ? 2010 microchip technology inc. ds70139g-page 13 dspic30f2011/2012/3012/3013 figure 1-2: dspic30f20 12 block diagram an8/oc1/rb8 an9/oc2/rb9 power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode & control osc1/clki mclr v dd , v ss an4/cn6/rb4 low-voltage detect uart1 timing generation an5/cn7/rb5 16 pch pcl program counter alu<16> 16 24 24 24 24 x data bus ir i 2 c? an6/ocfa/rb6 emud2/an7/rb7 pcu 12-bit adc timers cn18/rf5 sck1/int0/rf6 input capture module output compare module emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 emud3/an0/v ref +/cn2/rb0 portb pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 osc2/clko/rc15 cn17/rf4 av dd , av ss 16 16 16 16 16 portc portf 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (512 bytes) ram x data ram address latch address latch emuc2/ic1/int1/rd8 ic2/int2/rd9 16 emuc3/an1/v ref -/cn3/rb1 spi1 address latch program memory (12 kbytes) data latch 16 (512 bytes) dspic30f2011/2012/3012/3013 ds70139g-page 14 ? 2010 microchip technology inc. figure 1-3: dspic30f 3012 block diagram power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode & control osc1/clki mclr v dd , v ss pgd/emud/an4/u1tx/sdo1/scl/cn6/rb4 low-voltage detect uart1 timing generation pgc/emuc/an5/u1rx/sdi1/sda/cn7/r b5 16 pch pcl program counter alu<16> 16 24 24 24 24 x data bus ir i 2 c? an6/sck1/int0/ocfa/rb6 emud2/an7/oc2/ic2/int2/rb7 pcu 12-bit adc timers input capture module output compare module emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 portb portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 osc2/clko/rc15 av dd , av ss 16 16 16 16 16 portc 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (1 kbytes) ram x data (1 kbytes) ram address latch address latch emuc2/oc1/ic1/int1/rd0 16 spi1 address latch program memory (24 kbytes) data latch 16 data eeprom (1 kbytes) ? 2010 microchip technology inc. ds70139g-page 15 dspic30f2011/2012/3012/3013 figure 1-4: dspic30f30 13 block diagram an8/oc1/rb8 an9/oc2/rb9 power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode & control osc1/clki mclr v dd , v ss an4/cn6/rb4 low-voltage detect uart1, timing generation an5/cn7/rb5 16 pch pcl program counter alu<16> 16 24 24 24 24 x data bus ir i 2 c? an6/ocfa/rb6 emud2/an7/rb7 pcu 12-bit adc timers u2tx/cn18/rf5 sck1/int0/rf6 input capture module output compare module emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 emud3/an0/v ref +/cn2/rb0 portb pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 osc2/clko/rc15 u2rx/cn17/rf4 av dd , av ss uart2 16 16 16 16 16 portc portf 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (1 kbytes) ram x data ram address latch address latch emuc2/ic1/int1/rd8 ic2/int2/rd9 16 emuc3/an1/v ref -/cn3/rb1 spi1 16 (1 kbytes) address latch program memory (24 kbytes) data latch data eeprom (1 kbytes) dspic30f2011/2012/3012/3013 ds70139g-page 16 ? 2010 microchip technology inc. table 1-1 provides a brief description of device i/o pinouts and the functions that may be multiplexed to a port pin. multiple functions may exist on one port pin. when multiplexing occurs, the peripheral module?s functional requirements may force an override of the data direction of the port pin. table 1-1: pinout i/o descriptions pin name pin type buffer type description an0 - an9 i analog analog input channels. av dd p p positive supply for analog module. this pin must be connected at all times. av ss p p ground reference for analog module. this pin must be connected at all times. clki clko i o st/cmos ? external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to cryst al or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. cn0 - cn7 i st input change notification inputs. can be software programmed for internal weak pull-ups on all inputs. emud emuc emud1 emuc1 emud2 emuc2 emud3 emuc3 i/o i/o i/o i/o i/o i/o i/o i/o st st st st st st st st icd primary communication channel data input/output pin. icd primary communication cha nnel clock input/output pin. icd secondary communication channel data input/output pin. icd secondary communication channel clock input/output pin. icd tertiary communication channel data input/output pin. icd tertiary communication channel clock input/output pin. icd quaternary communication channel data input/output pin. icd quaternary communication ch annel clock input/output pin. ic1 - ic2 i st capture inputs 1 through 2. int0 int1 int2 i i i st st st external interrupt 0. external interrupt 1. external interrupt 2. lvdin i analog low-voltage detect reference voltage input pin. mclr i/p st master clear (reset) input or programming voltage input. this pin is an active-low reset to the device. oc1-oc2 ocfa o i ? st compare outputs 1 through 2. compare fault a input. osc1 osc2 i i/o st/cmos ? oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to cryst al or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. pgd pgc i/o i st st in-circuit serial programming? data input/output pin. in-circuit serial programming clock input pin. rb0 - rb9 i/o st portb is a bidirectional i/o port. rc13 - rc15 i/o st portc is a bidirectional i/o port. rd0, rd8-rd9 i/o st portd is a bidirectional i/o port. rf2 - rf5 i/o st portf is a bidirectional i/o port. sck1 sdi1 sdo1 ss1 i/o i o i st st ? st synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization. legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power ? 2010 microchip technology inc. ds70139g-page 17 dspic30f2011/2012/3012/3013 scl sda i/o i/o st st synchronous serial clock input/output for i 2 c?. synchronous serial data input/output for i 2 c. sosco sosci o i ? st/cmos 32 khz low-power oscillator crystal output. 32 khz low-power oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. t1ck t2ck i i st st timer1 external clock input. timer2 external clock input. u1rx u1tx u1arx u1atx u2rx u2tx i o i o i o st ? st ? st ? uart1 receive. uart1 transmit. uart1 alternate receive. uart1 alternate transmit. uart2 receive. uart2 transmit. v dd p ? positive supply for logic and i/o pins. v ss p ? ground reference for logic and i/o pins. v ref + i analog analog voltage reference (high) input. v ref - i analog analog voltage reference (low) input. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type description legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power dspic30f2011/2012/3012/3013 ds70139g-page 18 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 19 dspic30f2011/2012/3012/3013 2.0 cpu architecture overview this section is an overview of the cpu architecture of the dspic30f. the core has a 24-bit instruction word. the program counter (pc) is 23 bits wide with the least significant bit (lsb) always clear (see section 3.1 ?program address space? ). the most significant bit (msb) is ignored during normal program execution, except for certai n specialized instructions. thus, the pc can address up to 4m instruction words of user program space. an instruction prefetch mechanism helps maintain throughput. program loop constructs, free from loop count management overhead, are supported using the do and repeat instructions, both of which ar e interruptible at any point. 2.1 core overview the working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset registers. one work ing register (w15) operates as a software stack pointe r for interrupts and calls. the data space is 64 kbytes (32k words) and is split into two blocks, referred to as x and y data memory. each block has its own independent address genera- tion unit (agu). most in structions operate solely through the x memory, agu, which provides the appearance of a single unified data space. the multiply-accumulate ( mac ) class of dual source dsp instructions operate through both the x and y agus, splitting the data address space into two parts (see section 3.2 ?data address space? ). the x and y data space boundary is device specific and cannot be altered by the user. each data word consists of 2 bytes and most instructions can address data either as words or bytes. two ways to access data in program memory are: ? the upper 32 kbytes of data space memory can be mapped into the lower half (user space) of program space at any 16k program word boundary, defined by the 8-bit program space visibility page regist er (psvpag). thus any instruction can access program space as if it were data space, with a limitation that the access requires an additional cycle. only the lower 16 bits of each instructi on word can be accessed using this method. ? linear indirect access of 32k word pages within program space is also possible using any working register, via table read and write instructions. table read and write instructions can be used to access all 24 bits of an instruction word. overhead-free circular buffers (modulo addressing) are supported in both x and y address spaces. this is primarily intended to remove the loop overhead for dsp algorithms. the x agu also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering fo r radix-2 fft algorithms. refer to section 4.0 ?address generator units? for details on modulo and bit-reversed addressing. the core supports inherent (no operand), relative, literal, memory direct, register direct, register indirect, register offset and literal offset addressing modes. instructions are associated with pre-defined addressing modes, depending upon their functional requirements. for most instructions, the co re is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memo ry read per instruction cycle. as a result, 3 ope rand instructions are supported, allowing c = a+b operations to be exe- cuted in a single cycle. a dsp engine has been included to significantly enhance the core arithmetic capability and throughput. it features a high-speed 17-bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. data in the accumulator or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. the dsp instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. the mac class of instructions can concurrently fetch two data operands from memory while multiplying two w registers. to enable this concurrent fetching of data operands, the data space has been split for these instructions and linear is for all others. this has been achiev ed in a transparent and flexible manner, by dedicating certain working registers to each address space for the mac class of instructions. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). dspic30f2011/2012/3012/3013 ds70139g-page 20 ? 2010 microchip technology inc. the core does not support a multi-stage instruction pipeline. however, a single- stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycl e ahead of execution, in order to maximize available execution time. most instructions execute in a single cycle wi th certain exceptions. the core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. the exceptions consist of up to 8 traps (of which 4 are reserved) and 54 interrupts. each interrupt is prioritized based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ?natural order?. traps have fixed priorities ranging from 8 to 15. 2.2 programmer?s model the programmer?s model is shown in figure 2-1 and consists of 16 x 16-bit working registers (w0 through w15), 2 x 40-bit accumulators (acca and accb), status register (sr), data table page register (tblpag), program space visibility page register (psvpag), do and repeat registers (dostart, doend, dcount and rcount) and program coun- ter (pc). the working registers can act as data, address or offset registers. all registers are memory mapped. w0 acts as the w register for file register addressing. some of these registers have a shadow register asso- ciated with each of them, as shown in figure 2-1 . the shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. none of the shadow registers are accessible directly. the following rules apply for transfer of registers into and out of shadows. ? push.s and pop.s w0, w1, w2, w3, sr (dc, n, ov, z and c bits only) are transferred. ? do instruction dostart, doend, dcount shadows are pushed on loop start and popped on loop end. when a byte operation is performed on a working reg- ister, only the least significa nt byte (lsb) of the target register is affected. however, a benefit of memory mapped working registers is that both the least and most significant bytes (msb) can be manipulated through byte-wide data memory space accesses. 2.2.1 software stack pointer/ frame pointer the dspic ? dsc devices contain a software stack. w15 is the dedicated software stack pointer (sp), which is automatically modified by exception processing and subroutine calls and returns. however, w15 can be referenced by any instruction in the same manner as all other w registers. this simplifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames). w15 is initialized to 0x0800 during a reset. the user may reprogram the sp during initialization to any location within data space. w14 has been dedicated as a stack frame pointer, as defined by the lnk and ulnk instructions. however, w14 can be referenced by any instruction in the same manner as all other w registers. 2.2.2 status register the dspic dsc core has a 16-bit status register (sr), the lsb of which is re ferred to as the sr low byte (srl) and the msb as the sr high byte (srh). see figure 2-1 for sr layout. srl contains all the mcu alu operation status flags (including the z bit), as well as the cpu interrupt priority level status bits, ipl<2:0>, and the repeat active status bit, ra. during exception processing, srl is concatenated with t he msb of the pc to form a complete word value which is then stacked. the upper byte of the status register contains the dsp adder/subtracter status bits, the do loop active bit (da) and the digit carry (dc) status bit. 2.2.3 program counter the program counter is 23 bits wide; bit 0 is always clear. therefore, the pc can address up to 4m instruction words. note: in order to protect against misaligned stack accesses, w15< 0> is always clear. ? 2010 microchip technology inc. ds70139g-page 21 dspic30f2011/2012/3012/3013 figure 2-1: programmer?s model tabpag pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write-back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb psvpag 7 0 program space visibility page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c dspic30f2011/2012/3012/3013 ds70139g-page 22 ? 2010 microchip technology inc. 2.3 divide support the dspic dsc devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsi gned integer divide opera- tions, in the form of single instruction iterative divides. the following instructions and data sizes are supported: 1. divf - 16/16 signed fractional divide 2. div.sd - 32/16 signed divide 3. div.ud - 32/16 unsigned divide 4. div.s - 16/16 signed divide 5. div.u - 16/16 unsigned divide the 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sign-extended during the first iteration. the divide instructions must be executed within a repeat loop. any other form of execution (e.g., a series of discrete divide instructions) will not function correctly because the instruction flow depends on rcount. the divide instruction does not automatically set up the rcount value and it must, therefore, be explic itly and correctly specified in the repeat instruction, as shown in ta b l e 2 - 1 ( repeat executes the target inst ruction {operand value+1} times). the repeat loop count must be setup for 18 iterations of the div/divf instruction. thus, a complete divide operat ion requires 19 cycles. table 2-1: divide instructions note: the divide flow is interruptible; however, the user needs to save the context as appropriate. instruction function divf signed fractional divide: wm/wn w0; rem w1 div.sd signed divide: (wm+1:wm)/wn w0; rem w1 div.s signed divide: wm/wn w0; rem w1 div.ud unsigned divide: (wm+1:wm)/wn w0; rem w1 div.u unsigned divide: wm/wn w0; rem w1 ? 2010 microchip technology inc. ds70139g-page 23 dspic30f2011/2012/3012/3013 2.4 dsp engine the dsp engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). the dsp engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. these instructions are add, sub and neg . the dspic30f is a single-cycle instruction flow architecture, therefore, c oncurrent operation of the dsp engine with mcu instruction flow is not possible. however, some mcu alu and dsp engine resources may be used concurrently by the same instruction (e.g., ed, edac ). see ta b l e 2 - 2 . the dsp engine has several options selected through various bits in the cpu core configuration register (corcon), which are: 1. fractional or integer dsp multiply (if). 2. signed or unsigned dsp multiply (us). 3. conventional or convergent rounding (rnd). 4. automatic saturation on/off for acca (sata). 5. automatic saturation on/off for accb (satb). 6. automatic saturation on/off for writes to data memory (satdw). 7. accumulator satura tion mode selection (accsat). a block diagram of the dsp engine is shown in figure 2-2 . table 2-2: dsp instruction summary instruction algebraic operation acc wb? clr a = 0 yes ed a = (x ? y) 2 no edac a = a + (x ? y) 2 no mac a = a + (x * y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x ? y no mpy.n a = ? x ? y no msc a = a ? x ? y yes note: for corcon layout, see table 3-3 . dspic30f2011/2012/3012/3013 ds70139g-page 24 ? 2010 microchip technology inc. figure 2-2: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to / f r o m w a r r a y adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit ? 2010 microchip technology inc. ds70139g-page 25 dspic30f2011/2012/3012/3013 2.4.1 multiplier the 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are zero-extended into the 17th bit of the multiplier input value. signed operands are sign-extended into the 17th bit of the multiplier input value. t he output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits. integer data is inherently represented as a signed two?s complement value, where the msb is defined as a sign bit. generally speaking, the range of an n-bit two?s complement integer is -2 n-1 to 2 n-1 ? 1. for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff) including ? 0 ?. for a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,645 (0x7fff ffff). when the multiplier is configured for fractional multiplication, the data is represented as a two?s complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit two?s complement fraction with this implied radix point is -1.0 to (1 ? 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0x7fff) including ? 0 ? and has a precision of 3.01518x10 -5 . in fractional mode, the 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661 x 10 -10 . the same multiplier is used to support the mcu multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiplies. the mul instruction can be directed to use byte or word-sized operands. byte operands direct a 16-bit result. word operands direct a 32-bit result to the specified register(s) in the w array. 2.4.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre-accumulation source and post-accumulation destination. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled through the barrel shifter prior to accumulation. 2.4.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40- bit adder with an optional zero input into one side and either true or complement data into the other input. in the case of addition, the carry/borrow input is active high and the other input is true data (not complemented), whereas in the case of subtraction, the carry/borrow input is active low and the other input is complement ed. the adder/subtracter generates overflow status bits sa/sb and oa/ob, which are latched and reflected in the status register: ? overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. ? overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additional saturation block which controls accumulator data saturation if selected. it uses the result of the adder, the overflow status bits described above, and the mode control bits sata/b (corcon<7:6>) and accsat (corcon<4>) to determine when and to what value to saturate. six status register bits have been provided to support saturation and overflow. they are: ? oa: acca overflowed into guard bits ? ob: accb overflowed into guard bits ? sa: acca saturated (bit 31 overflow and saturation) or acca overflowed into guard bits and saturated (bit 39 overflow and saturation) ? sb: accb saturated (bit 31 overflow and saturation) or accb overflowed into guard bits and saturated (bit 39 overflow and saturation) ? oab: logical or of oa and ob ? sab: logical or of sa and sb the oa and ob bits are modified each time data passes through the adder/su btracter. when set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). the oa and ob bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (ovate, ovbte) in the intcon1 register (refer to section 8.0 ?interrupts? ) is set. this allows the user to take immediate action, for exampl e, to correct system gain. dspic30f2011/2012/3012/3013 ds70139g-page 26 ? 2010 microchip technology inc. the sa and sb bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated if saturation is enabled. when satura- tion is not enabled, sa and sb default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. if the covte bit in the intcon1 register is set, sa and sb bits generate an arithmetic warning trap when saturation is disabled. the overflow and saturation status bits can optionally be viewed in the status register (sr) as the logical or of oa and ob (in bit oab) and the logical or of sa and sb (in bit sab). this allows programmers to check one bit in the status register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. this would be useful for complex number arithmetic which typically uses both the accumulators. the device supports three saturation and overflow modes: 1. bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user. this is referred to as ?super saturation? and pr ovides protection against erroneous data or unexpected algorithm problems (e.g., gain calculations). 2. bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then loads the maximally posi- tive 1.31 value (0x007fffffff) or maximally negative 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user. when this saturation mode is in effect, the guard bits are not used, so the oa, ob or oab bits are never set. 3. bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit which remains set until cleared by the user. no saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 2.4.2.2 accumulator ?write-back? the mac class of instructions (with the exception of mpy, mpy.n, ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is no t targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: 1. w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. 2. [w13]+ = 2, register indirect with post-increment: the rounded contents of the non-target accumulator are written into the address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 2.4.2.3 round logic the round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value, which is passed to the data space write saturation logic. if rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded. conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the accxh word (bits 16 through 31 of the accumulator). if the accxl word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xffff (0x8000 included), accxh is incremented. if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. if this is the case, the lsb (bit 16 of the accumulator) of accxh is examined. if it is ? 1 ?, accxh is incremented. if it is ? 0 ?, accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate. the sac and sac.r instructions store either a truncated ( sac ) or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus (subject to data saturation, see section 2.4.2.4 ?data space write saturation? ). note that for the mac class of instructions, the accumulator write-back operation functions in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding. ? 2010 microchip technology inc. ds70139g-page 27 dspic30f2011/2012/3012/3013 2.4.2.4 data space write saturation in addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly. for input data greater than 0x007fff, data written to memory is forced to the maximum positive 1.15 value, 0x7fff. for input data less than 0xff8000, data writ ten to memory is forced to the maximum negative 1.15 value, 0x8000. the msb of the source (bit 39) is us ed to determine the sign of the operand being tested. if the satdw bit in the corco n register is not set, the input data is always passed through unmodified under all conditions. 2.4.3 barrel shifter the barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts , or up to 16-bit left shifts in a single cycle. the source can be either of the two dsp accumulators, or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. a negative value shifts the operand left. a value of ? 0 ? does not modify the operand. the barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for dsp shift operations and a 16-bit result for mcu shift operations. data from the x bus is presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 16 for left shifts. dspic30f2011/2012/3012/3013 ds70139g-page 28 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 29 dspic30f2011/2012/3012/3013 3.0 memory organization 3.1 program address space the program address space is 4m instruction words. the program space memory maps for the dspic30f2011/2012/3012/3013 devices is shown in figure 3-1 . program memory is addressable by a 24-bit value from either the 23-bit pc, table instruction effective address (ea), or data space ea, when program space is mapped into data space as defined by ta b l e 3 - 1 . note that the program space addr ess is incremented by two between successive program words in order to provide compatibility with data space addressing. user program space access is restricted to the lower 4m instruction word address range (0x000000 to 0x7ffffe) for all accesses other than tblrd/tblwt , which uses tblpag<7> to determine user or configu- ration space access. in table 3-1 , program space address construction, bit 23 allows access to the device id, the user id and the configuration bits. otherwise, bit 23 is always clear. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). dspic30f2011/2012/3012/3013 ds70139g-page 30 ? 2010 microchip technology inc. figure 3-1: program space memory maps reset - target address user memory space 000000 00007e 000002 000080 device configuration user flash program memory 002000 001ffe configuration memory space (4k instructions) 800000 f80000 registers f8000e f80010 devid (2) fefffe ff0000 fffffe reserved f7fffe reserved (read ? 0 ?s) 8005fe 800600 unitid (32 instr.) vector tables 8005be 8005c0 reset - goto instruction 000004 reserved 7ffffe reserved 000100 0000fe 000084 alternate vector table reserved interrupt vector table reset - target address user memory space 000000 00007e 000002 000080 device configuration user flash program memory 004000 003ffe configuration memory space data eeprom (8k instructions) (1 kbyte) 800000 f80000 registers f8000e f80010 devid (2) fefffe ff0000 fffffe reserved f7fffe reserved 7ffc00 7ffbfe (read ? 0 ?s) 8005fe 800600 unitid (32 instr.) vector tables 8005be 8005c0 reset - goto instruction 000004 reserved 7ffffe reserved 000100 0000fe 000084 alternate vector table reserved interrupt vector table dspic30f2011/2012 dspic30f3012/3013 ? 2010 microchip technology inc. ds70139g-page 31 dspic30f2011/2012/3012/3013 table 3-1: program space address construction figure 3-2: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access user 0 pc<22:1> 0 tblrd/tblwt user (tblpag<7> = 0 ) tblpag<7:0> data ea<15:0> tblrd/tblwt configuration (tblpag<7> = 1 ) tblpag<7:0> data ea<15:0> program space visibility user 0 psvpag<7:0> data ea<14:0> 0 program counter 23 bits 1 psvpag reg 8 bits ea 15 bits program using select tblpag reg 8 bits ea 16 bits using byte 24-bit ea 0 0 1 / 0 select user/ configuration table instruction program space counter using space select visibility note: program space visibility cannot be used to acce ss bits <23:16> of a word in program memory. dspic30f2011/2012/3012/3013 ds70139g-page 32 ? 2010 microchip technology inc. 3.1.1 data access from program memory using table instructions this architecture fetches 24-bit wide program memory. consequently, instructions are always aligned. however, as the architecture is modified harvard, data can also be present in program space. there are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16k word program space page into the upper half of data space (see section 3.1.2 ?data access from program memory using program space visibility? ). the tblrdl and tblwtl instructions offer a direct method of reading or writing the lsw of any address within program space, without going through data space. the tblrdh and tblwth instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which contains the lsw, and tblrdh and tblwth access the space which contains the msb. figure 3-2 shows how the ea is created for table operations and data space accesses (psv = 1 ). here, p<23:0> refers to a program space word, whereas d<15:0> refers to a data space word. a set of table instructions are provided to move byte or word-sized data to and from program space. see figure 3-4 and figure 3-5. 1. tblrdl: table read low word: read the ls word of the program address; p<15:0> maps to d<15:0>. byte: read one of the lsb of the program address; p<7:0> maps to the destination byte when byte select = 0 ; p<15:8> maps to the destination byte when byte select = 1 . 2. tblwtl: table write low (refer to section 5.0 ?flash program memory? for details on flash programming) 3. tblrdh: table read high word: read the ms word of the program address; p<23:16> maps to d<7:0>; d<15:8> will always be = 0 . byte: read one of the msb of the program address; p<23:16> maps to the destination byte when byte select = 0 ; the destination byte will always be = 0 when byte select = 1 . 4. tblwth: table write high (refer to section 5.0 ?flash program memory? for details on flash programming) figure 3-3: program data table access (lsw) 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) tblrdl.w tblrdl.b (wn<0> = 1) tblrdl.b (wn<0> = 0) ? 2010 microchip technology inc. ds70139g-page 33 dspic30f2011/2012/3012/3013 figure 3-4: program data table access (msb) 3.1.2 data access from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word program space page. this provides transparent acce ss of stored constant data from x data space without the need to use special instructions (i.e., tblrdl/h , tblwtl/h instructions). program space access through the data space occurs if the msb of the data space ea is set and program space visibility is enabled by setting the psv bit in the core control register (corcon). the functions of corcon are discussed in section 2.4 ?dsp engine? . data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. note that the upper half of addressable data space is always part of the x data space. therefore, when a dsp operation uses program space mapping to access this memory region, y data space should typically contain state (variable) data for dsp operations, whereas x data space should typically contain coefficient (constant) data. although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see figure 3-5 ), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits should be programmed to force an illegal instruction to maintain ma chine robustne ss. refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157) for details on instruction encoding. note that by incrementing the pc by 2 for each program memory word, the ls 15 bits of data space addresses directly map to the ls 15 bits in the corresponding program space addresses. the remaining bits are provided by the program space visibility page register, psvpag<7:0>, as shown in figure 3-5 . for instructions that use psv which are executed outside a repeat loop: ? the following instructions require one instruction cycle in addition to the specified execution time: - mac class of instructions with data operand prefetch - mov instructions - mov.d instructions ? all other instructions requ ire two instruction cycles in addition to the specified execution time of the instruction. for instructions that use psv which are executed inside a repeat loop: ? the following instances require two instruction cycles in addition to the specified execution time of the instruction: - execution in th e first iteration - execution in the last iteration - execution prior to exiting the loop due to an interrupt - execution upon re-entering the loop after an interrupt is serviced ? any other iteration of the repeat loop allow the instruction accessing data, using psv, to execute in a single cycle. 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) tblrdh.w tblrdh.b (wn<0> = 1) tblrdh.b (wn<0> = 0) note: psv access is temporar ily disabled during table reads/writes. dspic30f2011/2012/3012/3013 ds70139g-page 34 ? 2010 microchip technology inc. figure 3-5: data space window in to program space operation 23 15 0 psvpag (1) 15 15 ea<15> = 0 ea<15> = 1 16 data space ea data space program space 8 15 23 0x0000 0x8000 0xffff 0x00 0x001fff data read upper half of data space is mapped into program space 0x001200 address concatenation bset corcon,#2 ; set psv bit mov #0x0, w0 ; set psvpag register mov w0, psvpag mov 0x9200, w0 ; access program memory location ; using a data space access note 1: psvpag is an 8-bit register, containing bi ts <22:15> of the program space address. 0x000000 ? 2010 microchip technology inc. ds70139g-page 35 dspic30f2011/2012/3012/3013 3.2 data address space the core has two data spaces. the data spaces can be considered either separate (for some dsp instructions), or as one un ified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. 3.2.1 data space memory map the data space memory is split into two blocks, x and y data space. a key element of this architecture is that y space is a subset of x space, and is fully contained within x space. in order to provide an apparent linear addressing space, x and y spaces have contiguous addresses. when executing any instruction other than one of the mac class of instructions, the x block consists of the 64 kbyte data address space (including all y addresses). when executing one of the mac class of instructions, the x block consists of the 64 kbyte data address space, excluding the y address block (for data reads only). in other words, all other instructions regard the entire data memory as one composite address space. the mac class instructions extract the y address space from data space and address it using eas sourced from w10 and w11. the remaining x data space is addressed using w8 and w9. both address spaces are concurrently acce ssed only with the mac class instructions. the data space memory map for the dspic30f2011 and dspic30f2012 is shown in figure 3-6 . the data space memory map for the dspic30f3012 and dspic30f3013 is shown in figure 3-7 . figure 3-6: dspic30f2011/2012 data space memory map 0x0000 0x07fe 0x09fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0x09ff 0xffff 0x8001 0x8000 optionally mapped into program memory 0x0bff 0x0bfe 0x0c00 0x0c01 0x0801 0x0800 0x0a01 0x0a00 near data 0x1ffe 0x1fff 2 kbyte sfr space 1 kbyte sram space 8 kbyte space x data unimplemented (x) sfr space x data ram (x) y data ram (y) dspic30f2011/2012/3012/3013 ds70139g-page 36 ? 2010 microchip technology inc. figure 3-7: dspic30f3012/3013 data space memory map 0x0000 0x07fe 0x0bfe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0x0bff 0xffff 0x8001 0x8000 optionally mapped into program memory 0x0fff 0x0ffe 0x1000 0x1001 0x0801 0x0800 0x0c01 0x0c00 near data 0x1ffe 0x1fff 2 kbyte sfr space 2 kbyte sram space 8 kbyte space x data unimplemented (x) sfr space x data ram (x) y data ram (y) ? 2010 microchip technology inc. ds70139g-page 37 dspic30f2011/2012/3012/3013 figure 3-8: data space for mcu and dsp ( mac class) instructions example sfr space (y space) x space sfr space unused x space x space y space unused unused non- mac class ops (read/write) mac class ops (read) indirect ea using any w indirect ea using w8, w9 indirect ea using w10, w11 mac class ops (write) dspic30f2011/2012/3012/3013 ds70139g-page 38 ? 2010 microchip technology inc. 3.2.2 data spaces the x data space is used by all instructions and sup- ports all addressing modes. there are separate read and write data buses. the x read data bus is the return data path for all instructions that view data space as combined x and y address space. it is also the x address space data path for the dual operand read instructions ( mac class). the x write data bus is the only write path to data space for all instructions. the x data space also supports modulo addressing for all instructions, subject to addressing mode restric- tions. bit-reversed addressing is only supported for writes to x data space. the y data space is used in concert with the x data space by the mac class of instructions ( clr, ed, edac, mac, movsac, mpy, mpy.n and msc ) to provide two concurrent data read paths. no writes occur across the y bus. this class of instructions dedicates two w register pointers, w10 and w11, to always address y data space, independent of x data space, whereas w8 and w9 always address x data space. note that during accumulator write back, the data address space is considered a combination of x and y data spaces, so the write occurs across the x bus. consequently, the write can be to any address in the entire data space. the y data space can only be used for the data prefetch operation associated with the mac class of instructions. it also suppo rts modulo addressing for automated circular buffers. of course, all other instructions can access the y data address space through the x data path as part of the composite linear space. the boundary between the x and y data spaces is defined as shown in figure 3-7 and is not user programmable. should an ea point to data outside its own assigned address space, or to a location outside physical memory, an all zero word/byte is returned. for example, although y address space is visible by all non- mac instructions using any addressing mode, an attempt by a mac instruction to fetch data from that space using w8 or w9 (x space pointers) returns 0x0000. table 3-2: effect of invalid memory accesses all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes or 32k words. 3.2.3 data space width the core data width is 16 bits. all internal registers are organized as 16-bit wide words. data space memory is organized in byte addre ssable, 16-bit wide blocks. 3.2.4 data alignment to help maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic30f instruction set supports both word and byte operations. data is aligned in data memory and registers as words, but all data space eas resolve to bytes. data byte reads read the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the x data path (no byte accesses are possible from the y data path as the mac class of instruction can only fetch words). that is, data memory and registers are organized as two parallel byte wide entities with shared (word) address decode but separate write lines. data byte writes only write to the corresponding side of the array or register which matches the byte address. as a consequence of this byte accessibility, all effective address calculations (incl uding those generated by the dsp operations which are restricted to word-sized data) are internally scaled to step through word-aligned memory. for example, the core would recognize that post-modified register indirect addressing mode [ws++] results in a value of ws + 1 for byte operations and ws + 2 for word operations. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care should be taken when mixing byte and word operations, or translating from 8-bit mcu code. should a misaligned read or write be attempted, an address error trap is generated. if the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the instruction is executed, but the write does not occur. in either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address fault. figure 3-9: data alignment attempted operat ion data returned ea = an unimplemented address 0x0000 w8 or w9 used to access y data space in a mac instruction 0x0000 w10 or w11 used to access x data space in a mac instruction 0x0000 15 8 7 0 0001 0003 0005 0000 0002 0004 byte 1 byte 0 byte 3 byte 2 byte 5 byte 4 lsb msb ? 2010 microchip technology inc. ds70139g-page 39 dspic30f2011/2012/3012/3013 all byte loads into any w register are loaded into the lsb. the msb is not modified. a sign-extend (se) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, users can clear the msb of any w register by executing a zero-extend (ze) instru ction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the dsp instructions, operate only on words. 3.2.5 near data space an 8 kbyte near data space is reserved in x address memory space between 0x0000 and 0x1fff, which is directly addressable via a 13-bit absolute address field within all memory direct in structions. the remaining x address space and all of the y address space is addressable indirectly. additionally, the whole of x data space is addressable using mov instructions, which support memory direct addressing with a 16-bit address field. 3.2.6 software stack the dspic dsc devices contain a software stack. w15 is used as the stack pointer. the stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. it pre-decrements for stack pops and post-increments for stack pushes, as shown in figure 3-10 . note that for a pc push during any call instruction, the msb of th e pc is zero-extended before the push, ensuring that the msb is always clear. figure 3-10: call stack frame there is a stack pointer limit register (splim) associated with the st ack pointer. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word aligned. whenever an effective address (ea) is generated using w15 as a source or destination pointer, the address thus generated is compared with the value in splim. if the contents of the stack pointer (w15) and the splim reg- ister are equal, and a push operation is performed, a stack error trap does not occur. the stack error trap occurs on a subsequent push operation. thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in ram, initialize the splim with the value, 0x1ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800, thus preventing the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. note: a pc push during exception processing concatenates the srl register to the msb of the pc prior to the push. dspic30f2011/2012/3012/3013 ds70139g-page 40 ? 2010 microchip technology inc. table 3-3: core register map sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state w0 0000 w0/wreg 0000 0000 0000 0000 w1 0002 w1 0000 0000 0000 0000 w2 0004 w2 0000 0000 0000 0000 w3 0006 w3 0000 0000 0000 0000 w4 0008 w4 0000 0000 0000 0000 w5 000a w5 0000 0000 0000 0000 w6 000c w6 0000 0000 0000 0000 w7 000e w7 0000 0000 0000 0000 w8 0010 w8 0000 0000 0000 0000 w9 0012 w9 0000 0000 0000 0000 w10 0014 w10 0000 0000 0000 0000 w11 0016 w11 0000 0000 0000 0000 w12 0018 w12 0000 0000 0000 0000 w13 001a w13 0000 0000 0000 0000 w14 001c w14 0000 0000 0000 0000 w15 001e w15 0000 1000 0000 0000 splim 0020 splim 0000 0000 0000 0000 accal 0022 accal 0000 0000 0000 0000 accah 0024 accah 0000 0000 0000 0000 accau 0026 sign extension (acca<39>) accau 0000 0000 0000 0000 accbl 0028 accbl 0000 0000 0000 0000 accbh 002a accbh 0000 0000 0000 0000 accbu 002c sign extension (accb<39>) accbu 0000 0000 0000 0000 pcl 002e pcl 0000 0000 0000 0000 pch 0030 ? ? ? ? ? ? ? ? ?pch 0000 0000 0000 0000 tblpag 0032 ? ? ? ? ? ? ? ?tblpag 0000 0000 0000 0000 psvpag 0034 ? ? ? ? ? ? ? ? psvpag 0000 0000 0000 0000 rcount 0036 rcount uuuu uuuu uuuu uuuu dcount 0038 dcount uuuu uuuu uuuu uuuu dostartl 003a dostartl 0 uuuu uuuu uuuu uuu0 dostarth 003c ? ? ? ? ? ? ? ? ?dostarth 0000 0000 0uuu uuuu doendl 003e doendl 0 uuuu uuuu uuuu uuu0 doendh 0040 ? ? ? ? ? ? ? ? ? doendh 0000 0000 0uuu uuuu sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. ? 2010 microchip technology inc. ds70139g-page 41 dspic30f2011/2012/3012/3013 corcon 0044 ? ? ? us edt dl2 dl1 dl0 sata satb satdw accsat ipl3 psv rnd if 0000 0000 0010 0000 modcon 0046 xmoden ymoden ? ? bwm<3:0> ywm<3:0> xwm<3:0> 0000 0000 0000 0000 xmodsrt 0048 xs<15:1> 0 uuuu uuuu uuuu uuu0 xmodend 004a xe<15:1> 1 uuuu uuuu uuuu uuu1 ymodsrt 004c ys<15:1> 0 uuuu uuuu uuuu uuu0 ymodend 004e ye<15:1> 1 uuuu uuuu uuuu uuu1 xbrev 0050 bren xb<14:0> uuuu uuuu uuuu uuuu disicnt 0052 ? ? disicnt<13:0> 0000 0000 0000 0000 table 3-3: core register map (continued) sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 42 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 43 dspic30f2011/2012/3012/3013 4.0 address generator units the dspic dsc core contains two independent address generator units: the x agu and y agu. the y agu supports word-sized data reads for the dsp mac class of instructions only. the dspic dsc agus support three types of data addressing: ? linear addressing ? modulo (circular) addressing ? bit-reversed addressing linear and modulo data addressing modes can be applied to data space or program space. bit-reversed addressing is only applicable to data space addresses. 4.1 instruction addressing modes the addressing modes in ta b l e 4 - 1 form the basis of the addressing modes optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instructions are somewhat different from thos e in the other instruction types. 4.1.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space during file register operation. 4.1.2 mcu instructions the three-operand mcu instru ctions are of the form: operand 3 = operand 1 dspic30f2011/2012/3012/3013 ds70139g-page 44 ? 2010 microchip technology inc. 4.1.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions provide a great er degree of addressing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accu mulator instructions also support register indire ct with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? register indirect with register offset (indexed) ? register indirect with literal offset ? 8-bit literal ? 16-bit literal 4.1.4 mac instructions the dual source operand dsp instructions ( clr, ed, edac, mac, mpy, mpy.n, movsac and msc ), also referred to as mac instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. the two source operand prefet ch registers must belong to the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu. w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: ? register indirect ? register indirect post-modified by 2 ? register indirect post-modified by 4 ? register indirect post-modified by 6 ? register indirect with register offset (indexed) 4.1.5 other instructions besides the various addressing modes outlined above, some instructions use litera l constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. 4.2 modulo addressing modulo addressing is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can only be configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers) based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-2 length. as these buffers satisfy the start and the end address criteria, they can operate in a bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. however, the 4-bit wb (register offset) field is shared between both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing is only available for w9 (in x space) and w11 (in y space). ? 2010 microchip technology inc. ds70139g-page 45 dspic30f2011/2012/3012/3013 4.2.1 start and end address the modulo addressing scheme requires that a starting and an ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see table 3-3 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.2.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to specify the w address registers. the xwm and ywm fields select which registers operate with modulo addressing. if xwm = 15 , x ragu and x wagu modulo addressing is disabled. similarly, if ywm = 15 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 3-3 ). modulo addressing is enabled for x data space when xwm is set to any value other than ? 15 ? and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm), to which modulo addressing is to be applied, is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than ? 15 ? and the ymoden bit is set at modcon<14>. figure 4-1: modulo addressing operation example note: y space modulo addressing ea calculations assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100,w0 mov w0,xmodsrt ;set modulo start address mov #0x1163,w0 mov w0,modend ;set modulo end address mov #0x8001,w0 mov w0,modcon ;enable w1, x agu for modulo mov #0x0000,w0 ;w0 holds buffer fill value mov #0x1110,w1 ;point w1 to buffer do again,#0x31 ;fill the 50 buffer locations mov w0,[w1++] ;fill the next location again: inc w0,w0 ;increment the fill value dspic30f2011/2012/3012/3013 ds70139g-page 46 ? 2010 microchip technology inc. 4.2.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. it is important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal to). address changes may, therefore, jump beyond boundaries and still be adjusted correctly. 4.3 bit-reversed addressing bit-reversed addressing is intended to simplify data re-ordering for radix-2 fft al gorithms. it is supported by the x agu for data writes only. the modifier, which may be a constant value or register contents, is regarded as havi ng its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.3.1 bit-reverse d addressing implementation bit-reversed addressing is enabled when: ? bwm (w register selection) in the modcon reg- ister is any value other than ? 15 ? (the stack cannot be accessed using bit-reversed addressing) and ? the bren bit is set in the xbrev register and ? the addressing mode used is register indirect with pre-increment or post-increment. if the length of a bit-reversed buffer is m = 2 n bytes, then the last ?n? bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier or ?pivot point? which is typically a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is only executed for register indirect with pre-increment or post-increment addressing and word-sized data writes. it does not function for any other addressing mode or for byte-sized data. normal addresses are generated instead. when bit-reversed ad dressing is active, the w address pointer is always added to the address modifier (xb) and the of fset associated with the register indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren bit (xbrev<15>), then a write to the xbrev register should not be immediately followed by an indirect read operatio n using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre-modify or post-modify addressing mode is used to compute the ea. when an address offset (e.g., [w7+w2]) is used, modulo address correction is performed, but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. in the event that the user attempts to do this, bit-reversed address- ing assumes priority when active for the x wagu, and x wagu modulo addressing is disabled. however, modulo addressing continues to function in the x ragu. ? 2010 microchip technology inc. ds70139g-page 47 dspic30f2011/2012/3012/3013 figure 4-2: bit-reversed address example table 4-2: bit-reversed ad dress sequence (16-entry) table 4-3: bit-reversed address modifier values for xbrev register normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 buffer size (words) xb<14:0> bit-reversed address modifier value 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point dspic30f2011/2012/3012/3013 ds70139g-page 48 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 49 dspic30f2011/2012/3012/3013 5.0 flash program memory the dspic30f family of devices contains internal program flash memory for ex ecuting user code. there are two methods by which the user can program this memory: 1. run-time self-programming (rtsp) 2. in-circuit serial programming? (icsp?) 5.1 in-circuit serial programming (icsp) dspic30f devices can be serially programmed while in the end application circuit. this is simply done with two lines for programming clock and programming data (which are named pgc and pgd respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unp rogrammed devices, and then program the microcontro ller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 5.2 run-time self-programming (rtsp) rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 32 instructions (96 bytes) at a time. 5.3 table instruction operation summary the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in word or byte mode. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can access program memory in word or byte mode. a 24-bit program memory address is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w regist er specified in the table instruction, as shown in figure 5-1 . figure 5-1: addressing for table and nvm registers note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). 0 program counter 24 bits nvmadru reg 8 bits 16 bits program using tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 1/0 0 1/0 select table instruction nvmadr addressing counter using nvmadr reg ea user/configuration space select dspic30f2011/2012/3012/3013 ds70139g-page 50 ? 2010 microchip technology inc. 5.4 rtsp operation the dspic30f flash program memory is organized into rows and panels. each row consists of 32 instructions or 96 bytes. each panel consists of 128 rows or 4k x 24 instructions. rtsp allows the user to erase one row (32 instructions) at a time and to program four instructions at one time. rtsp may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary. each panel of program memory contains write latches that hold 32 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the panel write latches. the data to be programmed into the panel is loaded in sequential order into the write latches; instruction 0 , instruction 1 , etc. the instruction words loaded must always be from a 32 address boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the write latches. programming is performed by setting the special bits in the nvmcon register. 32 tblwtl and four tblwth instructions are required to load the 32 instructions. if multiple panel programming is required, the table pointer needs to be changed and the next set of multiple write latches written. all of the table write operat ions are single-word writes (2 instruction cycles), because only the table latches are written. a programming cycle is required for programming each row. the flash program memory is readable, writable and erasable during normal oper ation over the entire v dd range. 5.5 control registers the four sfrs used to read and write the program flash memory are: ?nvmcon ? nvmadr ? nvmadru ? nvmkey 5.5.1 nvmcon register the nvmcon register contro ls which blocks are to be erased, which memory type is to be programmed, and start of the programming cycle. 5.5.2 nvmadr register the nvmadr register is used to hold the lower two bytes of the effective a ddress. the nvmadr register captures the ea<15:0> of the last table instruction that has been executed and selects the row to write. 5.5.3 nvmadru register the nvmadru register is used to hold the upper byte of the effective addre ss. the nvmadru register captures the ea<23:16> of th e last table instruction that has been executed. 5.5.4 nvmkey register nvmkey is a write-only regist er that is used for write protection. to start a programming or an erase sequence, the user must c onsecutively write 0x55 and 0xaa to the nvmkey register. refer to section 5.6 ?programming operations? for further details. note: the user can also directly write to the nvmadr and nvmadru registers to specify a program memory address for erasing or programming. ? 2010 microchip technology inc. ds70139g-page 51 dspic30f2011/2012/3012/3013 5.6 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. a programming operation is nominally 2 msec in duration and the processor stalls (waits) until the operation is finished. setting the wr bit (nvmcon<15>) starts the operation and the wr bit is automatically cleared when the operation is finished. 5.6.1 programming algorithm for program flash the user can erase or program one row of program flash memory at a time. the general process is: 1. read one row of program flash (32 instruction words) and store into data ram as a data ?image?. 2. update the data image with the desired new data. 3. erase program flash row. a) set up nvmcon register for multi-word, program flash, erase, and set wren bit. b) write address of row to be erased into nvmadru/nvmdr. c) write 0x55 to nvmkey. d) write 0xaa to nvmkey. e) set the wr bit. this begins erase cycle. f) cpu stalls for the duration of the erase cycle. g) the wr bit is cleared when erase cycle ends. 4. write 32 instruction words of data from data ram ?image? into the program flash write latches. 5. program 32 instruction words into program flash. a) set up nvmcon register for multi-word, program flash, program, and set wren bit. b) write 0x55 to nvmkey. c) write 0xaa to nvmkey. d) set the wr bit. this begins program cycle. e) cpu stalls for duration of the program cycle. f) the wr bit is cleared by the hardware when program cycle ends. 6. repeat steps 1 through 5 as needed to program desired amount of program flash memory. 5.6.2 erasing a row of program memory example 5-1 shows a code sequence that can be used to erase a row (32 instructions) of program memory. example 5-1: erasing a row of program memory ; setup nvmcon for erase operation, multi word write ; program memory selected, and writes enabled mov #0x4041,w0 ; mov w0 , nvmcon ; init nvmcon sfr ; init pointer to row to be erased mov #tblpage(prog_addr),w0 ; mov w0 , nvmadru ; initialize pm page boundary sfr mov #tbloffset(prog_addr),w0 ; intialize in-page ea[15:0] pointer mov w0, nvmadr ; initialize nvmadr sfr disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted dspic30f2011/2012/3012/3013 ds70139g-page 52 ? 2010 microchip technology inc. 5.6.3 loading write latches example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 tblwtl and 32 tblwth instructions are needed to load the write latches selected by the table pointer. 5.6.4 initiating the programming sequence for protection, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s as shown in example 5-3 . example 5-2: loading write latches example 5-3: initiating a programming sequence ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000,w0 ; mov w0 , tblpag ; initialize pm page boundary sfr mov #0x6000,w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0,w2 ; mov #high_byte_0,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1,w2 ; mov #high_byte_1,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2,w2 ; mov #high_byte_2,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ? ? ? ; 31st_program_word mov #low_word_31,w2 ; mov #high_byte_31,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch note: in example 5-2 , the contents of the upper byte of w3 has no effect. disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted ? 2010 microchip technology inc. ds70139g-page 53 dspic30f2011/2012/3012/3013 table 5-1: nvm register map file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ?twri ? progop<6:0> 0000 0000 0000 0000 nvmadr 0762 nvmadr<15:0> uuuu uuuu uuuu uuuu nvmadru 0764 ? ? ? ? ? ? ? ? nvmadr<23:16> 0000 0000 uuuu uuuu nvmkey 0766 ? ? ? ? ? ? ? ?key<7:0> 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 54 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 55 dspic30f2011/2012/3012/3013 6.0 data eeprom memory the data eeprom memory is readable and writable during normal operation over the entire v dd range. the data eeprom memory is di rectly mapped in the program memory address space. the four sfrs used to read and write the program flash memory are used to access data eeprom memory, as well. as described in section 5.5 ?control registers? , these registers are: ?nvmcon ? nvmadr ? nvmadru ? nvmkey the eeprom data memory allows read and write of single words and 16-word blocks. when interfacing to data memory, nvmadr, in conjunction with the nvmadru register, are used to address the eeprom location being accessed. tblrdl and tblwtl instructions are used to read and write data eeprom. the dspic30f devices have up to 8 kbytes (4k words) of data eeprom with an address range from 0x7ff000 to 0x7ffffe. a word write operation should be preceded by an erase of the corresponding memory location(s). the write typically requires 2 ms to complete, but the write time varies with voltage and temperature. a program or erase operation on the data eeprom does not stop the instruction flow. the user is responsible for waiting for the appropriate duration of time before initiating a nother data eeprom write/ erase operation. attempti ng to read the data eeprom while a programming or erase operation is in progress results in unspecified data. control bit wr initiates write operations similar to program flash writes. this bit cannot be cleared, only set, in software. they are cleared in hardware at the completion of the write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, allows a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit and rewrite the location. the address register nvmadr remains unchanged. 6.1 reading the data eeprom a tblrd instruction reads a word at the current program word address. this example uses w0 as a pointer to data eeprom. the result is placed in register w4 as shown in example 6-1 . example 6-1: data eeprom read note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). note: interrupt flag bit nvmif in the ifs0 register is set when write is complete. it must be cleared in software. mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag tblrdl [ w0 ], w4 ; read data eeprom dspic30f2011/2012/3012/3013 ds70139g-page 56 ? 2010 microchip technology inc. 6.2 erasing data eeprom 6.2.1 erasing a block of data eeprom in order to erase a block of data eeprom, the nvmadru and nvmadr registers must initially point to the block of memory to be erased. configure nvmcon for erasing a block of data eeprom and set the wr and wren bits in the nvmcon register. setting the wr bit initiates the erase, as shown in example 6-2 . example 6-2: data eeprom block erase 6.2.2 erasing a word of data eeprom the nvmadru and nvmadr registers must point to the block. select wr a block of data flash and set the wr and wren bits in the nvmcon register. setting the wr bit initiates the erase, as shown in example 6-3 . example 6-3: data eeprom word erase ; select data eeprom block, wr, wren bits mov #0x4045,w0 mov w0 , nvmcon ; initialize nvmcon sfr ; start erase cycle by setting wr after writing key sequence disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; initiate erase sequence nop nop ; erase cycle will complete in 2ms. cpu is not stalled for the data erase cycle ; user can poll wr bit, use nvmif or timer irq to determine erasure complete ; select data eeprom word, wr, wren bits mov #0x4044,w0 mov w0 , nvmcon ; start erase cycle by setting wr after writing key sequence disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; initiate erase sequence nop nop ; erase cycle will complete in 2ms. cpu is not stalled for the data erase cycle ; user can poll wr bit, use nvmif or timer irq to determine erasure complete ? 2010 microchip technology inc. ds70139g-page 57 dspic30f2011/2012/3012/3013 6.3 writing to the data eeprom to write an eeprom data location, the following sequence must be followed: 1. erase data eeprom word. a) select word, data eeprom erase, and set wren bit in nvmcon register. b) write address of word to be erased into nvmadr. c) enable nvm interrupt (optional). d) write 0x55 to nvmkey. e) write 0xaa to nvmkey. f) set the wr bit. this begins erase cycle. g) either poll nvmif bit or wait for nvmif interrupt. h) the wr bit is cleared when the erase cycle ends. 2. write data word in to data eeprom write latches. 3. program 1 data word into data eeprom. a) select word, data eeprom program, and set wren bit in nvmcon register. b) enable nvm write done interrupt (optional). c) write 0x55 to nvmkey. d) write 0xaa to nvmkey. e) set the wr bit. this begins program cycle. f) either poll nvmif bit or wait for nvm interrupt. g) the wr bit is cleared when the write cycle ends. the write does not initiate if the above sequence is not exactly followed (write 0x55 to nvmkey, write 0xaa to nvmcon, then set wr bit) fo r each word. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in nvmcon must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code execution. the wren bit should be kept clear at all times except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit does not affect the current write cycle. the wr bit is inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruction. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the nonvolatile memory write complete interrupt flag bi t (nvmif) is set. the user may either enable this interrupt or poll this bit. nvmif must be cleared by software. 6.3.1 writing a word of data eeprom once the user has erased the word to be programmed, then a table write instruction is used to write one write latch, as shown in example 6-4 . 6.3.2 writing a block of data eeprom to write a block of data eeprom, write to all sixteen latches first, then set the nvmcon register and program the block. example 6-4: data eeprom word write ; point to data memory mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #low(word),w2 ; get data tblwtl w2 , [ w0] ; write data ; the nvmadr captures last table access address ; select data eeprom for 1 word op mov #0x4004,w0 mov w0 , nvmcon ; operate key to allow write operation disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; initiate program sequence nop nop ; write cycle will complete in 2ms. cpu is not stalled for the data write cycle ; user can poll wr bit, use nvmif or timer irq to determine write complete dspic30f2011/2012/3012/3013 ds70139g-page 58 ? 2010 microchip technology inc. example 6-5: data eeprom block write 6.4 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared; also, the power-up timer prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #data1,w2 ; get 1st data tblwtl w2 , [ w0]++ ; write data mov #data2,w2 ; get 2nd data tblwtl w2 , [ w0]++ ; write data mov #data3,w2 ; get 3rd data tblwtl w2 , [ w0]++ ; write data mov #data4,w2 ; get 4th data tblwtl w2 , [ w0]++ ; write data mov #data5,w2 ; get 5th data tblwtl w2 , [ w0]++ ; write data mov #data6,w2 ; get 6th data tblwtl w2 , [ w0]++ ; write data mov #data7,w2 ; get 7th data tblwtl w2 , [ w0]++ ; write data mov #data8,w2 ; get 8th data tblwtl w2 , [ w0]++ ; write data mov #data9,w2 ; get 9th data tblwtl w2 , [ w0]++ ; write data mov #data10,w2 ; get 10th data tblwtl w2 , [ w0]++ ; write data mov #data11,w2 ; get 11th data tblwtl w2 , [ w0]++ ; write data mov #data12,w2 ; get 12th data tblwtl w2 , [ w0]++ ; write data mov #data13,w2 ; get 13th data tblwtl w2 , [ w0]++ ; write data mov #data14,w2 ; get 14th data tblwtl w2 , [ w0]++ ; write data mov #data15,w2 ; get 15th data tblwtl w2 , [ w0]++ ; write data mov #data16,w2 ; get 16th data tblwtl w2 , [ w0]++ ; write data. the nvmadr captures last table access address. mov #0x400a,w0 ; select data eeprom for multi word op mov w0 , nvmcon ; operate key to allow program operation disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start write cycle nop nop ? 2010 microchip technology inc. ds70139g-page 59 dspic30f2011/2012/3012/3013 7.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared between the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 7.1 parallel i/o (pio) ports when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three r egisters directly associated with the operation of the por t pin. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx), read the latch. writes to the latch, write the latch (latx). reads from the port (portx), read the port pins and writes to the port pins, write the latch (latx). any bit and its associated data and control registers that are not valid for a pa rticular device are disabled. that means the corresponding latx and trisx registers and the port pin read as zeros. when a pin is shared wit h another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competin g source of outputs. a parallel i/o (pio) port that shares a pin with a peripheral is, in general, subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pad cell. figure 7-1 illustrates how ports are shared with other peripherals and the associated i/o cell (pad) to which they are connected. the format of the registers for the shared ports, (portb, portc, portd and portf) are shown in table 7-1 through ta b l e 7 - 6 . figure 7-1: block diagram of a shared port structure note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual ? (ds70046). note: the actual bits in use vary between devices. q d ck wr lat + tris latch i/o pad wr port data bus q d ck data latch read lat read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o cell peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable dspic30f2011/2012/3012/3013 ds70139g-page 60 ? 2010 microchip technology inc. 7.2 configuring analog port pins the use of the adpcfg and tr is registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) is converted. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume the current that exceeds device specifications. 7.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be a nop . example 7-1: port write/read example mov #0xf0, w0 ; configure portb<7:4> ; as inputs mov w0, trisb ; and portb<3:0> as outputs nop ; additional instruction cycle btss portb, #7 ; bit test rb7 and skip if set ? 2010 microchip technology inc. ds70139g-page 61 dspic30f2011/2012/3012/3013 table 7-1: portb register ma p for dspic30f2011/3012 table 7-2: portb register ma p for dspic30f2012/3013 table 7-3: portc register map for dspic30f2011/2012/3012/3013 table 7-4: portd register ma p for dspic30f2011/3012 sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisb 02c6 ? ? ? ? ? ? ? ? trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 0000 0000 1111 1111 portb 02c8 ? ? ? ? ? ? ? ? rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 0000 0000 0000 0000 latb 02cb ? ? ? ? ? ? ? ? latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisb 02c6 ? ? ? ? ? ? trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 0000 0011 1111 1111 portb 02c8 ? ? ? ? ? ? rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 0000 0000 0000 0000 latb 02cb ? ? ? ? ? ? latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisc 02cc trisc15 trisc14 trisc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 1110 0000 0000 0000 portc 02ce rc15 rc14 rc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 latc 02d0 latc15 latc14 latc13 ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisd 02d2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?trisd0 0000 0000 0000 0001 portd 02d4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rd0 0000 0000 0000 0000 latd 02d6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?latd0 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? ? 2010 microchip technology inc. ds70139g-page 62 dspic30f2011/2012/3012/3013 table 7-5: portd register ma p for dspic30f2012/3013 table 7-6: portf register map for dspic30f2012/3013 sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisd 02d2 ? ? ? ? ? ? trisd9 trisd8 ? ? ? ? ? ? ? ? 0000 0011 0000 0000 portd 02d4 ? ? ? ? ? ? rd9 rd8 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 latd 02d6 ? ? ? ? ? ?latd9latd8 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisf 02de ? ? ? ? ? ? ? ? ? trisf6 trisf5 trisf4 trisf3 trisf2 ? ? 0000 0000 0111 1100 portf 02e0 ? ? ? ? ? ? ? ? ? rf6 rf5 rf4 rf3 rf2 ? ? 0000 0000 0000 0000 latf 02e2 ? ? ? ? ? ? ? ? ? latf6 latf5 latf4 latf3 latf2 ? ? 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note: the dspic30f2011/3012 devic es do not have trisf, portf, or latf. ? 2010 microchip technology inc. ds70139g-page 63 dspic30f2011/2012/3012/3013 7.3 input change notification module the input change notification module provides the dspic30f devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins. this module is capable of detecting input change of states even in sleep mode, when the clocks are disabled. there are up to 10 external signals (cn0 through cn7, cn17 and cn18) that may be selected (enabled) for generating an interrupt request on a change of state. table 7-7: input change notification register map for dspic30f2011/3012 (bits 7-0) table 7-8: input change notifi cation register map for ds pic30f2012/3013 (bits 7-0) sfr name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state cnen1 00c0 cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 0000 0000 0000 cnen2 00c2 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 cnpu1 00c4 cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 0000 0000 0000 cnpu2 00c6 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? sfr name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state cnen1 00c0 cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 0000 0000 0000 cnen2 00c2 ? ? ? ? ? cn18ie cn17ie ? 0000 0000 0000 0000 cnpu1 00c4 cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 0000 0000 0000 cnpu2 00c6 ? ? ? ? ? cn18pue cn17pue ? 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 64 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 65 dspic30f2011/2012/3012/3013 8.0 interrupts the dspic30f sensor family has up to 21 interrupt sources and 4 processor exceptions (traps) which must be arbitrated based on a priority scheme. the cpu is responsible for reading the interrupt vector table (ivt) and transferring the address contained in the interrupt vector to the program counter. the interrupt vector is transferred from the program data bus into the program counter via a 24-bit wide multiplexer on the input of the program counter. the interrupt vector table (ivt) and alternate interrupt vector table (aivt) are placed near the beginning of program memory (0x000004). the ivt and aivt are shown in figure 8-1 . the interrupt controller is responsible for pre-processing the interrupts and processor exceptions before they are presented to the processor core. the peripheral interrupts and traps are enabled, prioritized and controlled using centralized special function registers (sfrs): ? ifs0<15:0>, ifs1<15:0>, ifs2<15:0> all interrupt request flags are maintained in these three registers. the flags are set by their respective peripherals or external signals and they are cleared via software. ? iec0<15:0>, iec1<15:0>, iec2<15:0> all interrupt enable control bits are maintained in these three registers. th ese control bits are used to individually enable interrupts from the peripherals or external signals. ? ipc0<15:0> through ipc10<7:0> the user assignable priority level associated with each of these 41 interrupts is held centrally in these eleven registers. ?ipl<3:0> the current cpu priority level is explicitly stored in the ipl bits. ipl<3> is present in the corcon register, whereas ipl<2: 0> are present in the status register (sr) in the processor core. ? intcon1<15:0>, intcon2<15:0> global interrupt control functions are derived from these two registers. intcon1 contains the control and status flags for the processor exceptions. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate vector table. all interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, through the ipcx registers. each interrupt source is a ssociated with an interrupt vector, as shown in ta b l e 8 - 1 . levels 7 and 1 represent the highest and lowest maskable priorities, respec- tively. if the nstdis bit (intcon1<15>) is set, nesting of interrupts is prevented. thus, if an interrupt is currently being serviced, processing of a new interrupt is prevented even if the new inte rrupt is of higher priority than the one currently being serviced. certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupt-on-change, etc. control of these features remains within the peripheral module which generates the interrupt. the disi instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instructions, during which the disi bit (intcon2<14>) remains set. when an interrupt is serviced, the pc is loaded with the address stored in the vector location in program memory that corresponds to the interrupt. there are 63 different vectors within the ivt (refer to ta b l e 8 - 1 ). these vectors are contained in locations 0x000004 through 0x0000fe of program memory (refer to ta b l e 8 - 1 ). these locations contain 24-bit addresses, and in order to preserve robustness, an address error trap takes place if the pc attempts to fetch any of these words during normal execution. this prevents execution of random data as a result of accidentally decrementing a pc into vector space, accidentally mapping a data space address into vector space, or the pc rolling over to 0x000000 after reaching the end of implemented program memory space. execution of a goto instruction to this vector space also generates an address error trap. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit. user software should en sure the appropriate interrupt flag bits are clear prior to enabling an interrupt. note: assigning a priority level of ? 0 ? to an interrupt source is equivalent to disabling that interrupt. note: the ipl bits become read-only whenever the nstdis bit has been set to ? 1 ?. dspic30f2011/2012/3012/3013 ds70139g-page 66 ? 2010 microchip technology inc. 8.1 interrupt priority the user-assignable interrupt priority bits (ip<2:0>) for each individual interrupt source are located in the ls 3 bits of each nibble within the ipcx register(s). bit 3 of each nibble is not used and is read as a ? 0 ?. these bits define the priority level assigned to a particular interrupt by the user. natural order priority is determined by the position of an interrupt in the vector table, and only affects interrupt operation when multiple interrupts with the same user-assigned priority become pending at the same time. table 8-1 lists the interrupt numbers and interrupt sources for the dspi c30f2011/2012/3012/3013 devices and their associated vector numbers. the ability for the user to assign every interrupt to one of seven priority levels m eans that the user can assign a very high overall priority level to an interrupt with a low natural order priority. for example, the plvd (low voltage detect) can be given a priority of 7. the int0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. table 8-1: interrupt vector table note: the user-assignable priority levels start at 0 as the lowest priority and level 7 as the highest priority. note 1: the natural order priority scheme has 0 as the highest priority and 53 as the lowest priority. 2: the natural order priority number is the same as the int number. interrupt number vector number interrupt source highest natural order priority 0 8 int0 ? external interrupt 0 1 9 ic1 ? input capture 1 2 10 oc1 ? output compare 1 3 11 t1 ? timer 1 4 12 ic2 ? input capture 2 5 13 oc2 ? output compare 2 6 14 t2 ? timer2 7 15 t3 ? timer3 816spi1 9 17 u1rx ? uart1 receiver 10 18 u1tx ? uart1 transmitter 11 19 adc ? adc convert done 12 20 nvm ? nvm write complete 13 21 si2c ? i 2 c? slave interrupt 14 22 mi2c ? i 2 c master interrupt 15 23 input change interrupt 16 24 int1 ? external interrupt 1 17-22 25-30 reserved 23 31 int2 ? external interrupt 2 24 32 u2rx (1) ? uart2 receiver 25 33 u2tx (1) ? uart2 transmitter 26-41 34-49 reserved 42 50 lvd ? low-voltage detect 43-53 51-61 reserved lowest natural order priority note 1: only the dspic30f3013 has uart2 and the u2rx, u2tx interrupts. these locations are reserved for the dspic30f2011/2012/3012. ? 2010 microchip technology inc. ds70139g-page 67 dspic30f2011/2012/3012/3013 8.2 reset sequence a reset is not a true exception because the interrupt controller is not involved in the reset process. the processor initializes its regist ers in response to a reset which forces the pc to zero. the processor then begins program execution at location 0x000000. a goto instruction is stored in the first program memory location immediately followed by the address target for the goto instruction. the processor executes the goto to the specified address a nd then begins operation at the specified target (start) address. 8.2.1 reset sources in addition to external reset and power-on reset (por), there are six sources of error conditions which ?trap? to the reset vector. ? watchdog time-out: the watchdog has timed out, indicating that the processor is no longer executing the correct flow of code. ? uninitialized w register trap: an attempt to use an uninitialized w register as an address pointer causes a reset. ? illegal instruction trap: attempted execution of any unused opcodes results in an illegal instruction trap. note that a fetch of an illegal instruction does not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change. ? brown-out reset (bor): a momentary dip in the power supply to the device has been detected which may result in malfunction. ? trap lockout: occurrence of multiple trap conditions simultaneously causes a reset. 8.3 traps traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in figure 8-1 . they are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. note that many of these tr ap conditions can only be detected when they occur. consequently, the questionable instruction is allowed to complete prior to trap exception processing. if the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected. there are eight fixed priority levels for traps: level 8 through level 15, which implies that the ipl3 is always set during processing of a trap. if the user is not currently executing a trap, and he sets the ipl<3:0> bits to a value of ? 0111 ? (level 7), then all interrupts are disabled, but traps can still be processed. 8.3.1 trap sources the following traps are provided with increasing priority. however, since all traps can be nested, priority has little effect. math error trap: the math error trap executes under the following four circumstances: 1. if an attempt is made to divide by zero, the divide operation is aborted on a cycle boundary and the trap is taken. 2. if enabled, a math error trap is taken when an arithmetic operation on either accumulator a or b causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. if enabled, a math error trap is taken when an arithmetic operation on either accumulator a or b causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. if the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap occurs. note: if the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the address of a default handler that contains the reset instruc- tion. if, on the other hand, one of the vec- tors containing an invalid address is called, an address error trap is generated. dspic30f2011/2012/3012/3013 ds70139g-page 68 ? 2010 microchip technology inc. address error trap: this trap is initiated when any of the following circumstances occurs: 1. a misaligned data word access is attempted. 2. a data fetch from our unimplemented data memory location is attempted. 3. a data access of an unimplemented program memory location is attempted. 4. an instruction fetch from vector space is attempted. 5. execution of a ? bra #litera l? instruction or a ? goto #literal ? instruction, where literal is an unimplemented program memory address. 6. executing instructions after modifying the pc to point the unimplemented program memory addresses. the pc may be modified by loading a value into the stack and executing a return instruction. stack error trap: this trap is initiated under the following conditions: ? the stack pointer is loaded with a value which is greater than the (user programmable) limit value written into the splim register (stack overflow). ? the stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow). oscillator fail trap: this trap is initiated if the external oscillator fails and operation becomes reliant on an internal rc backup. 8.3.2 hard and soft traps it is possible that multip le traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). in such a case, the fixed priority shown in figure 8-2 is implemented, which may require the user to check if other traps are pending, in order to completely correct the fault. soft traps include exceptions of priority level 8 through level 11, inclusive. the arithmetic error trap (level 11) falls into this category of traps. hard traps include exceptions of priority level 12 through level 15, inclusive. the address error (level 12), stack error (level 13) and oscillator error (level 14) traps fall into this category. each hard trap that occurs must be acknowledged before code execution of any type can continue. if a lower priority hard trap occurs while a higher priority trap is pending, acknowledged, or is being processed, a hard trap conflict occurs. the device is automatically reset in a hard trap conflict condition. the trapr stat us bit (rcon<15>) is set when the reset occurs, so that the condition may be detected in software. note: in the mac class of instru ctions, wherein the data space is split into x and y data space, unimplemented x space includes all of y space, and unimplemented y space includes all of x space. ? 2010 microchip technology inc. ds70139g-page 69 dspic30f2011/2012/3012/3013 figure 8-1: trap vectors 8.4 interrupt sequence all interrupt event flags are sampled in the beginning of each instruction cycle by the ifsx registers. a pending interrupt request (irq) is indicated by the flag bit being equal to a ? 1 ? in an ifsx register. the irq causes an interrupt to occur if the corresponding bit in the interrupt enable (iecx) register is set. for the remainder of the instruction cycle, the priorities of all pending interrupt requests are evaluated. if there is a pending irq with a priority level greater than the current processor priority level in the ipl bits, the processor is interrupted. the processor then stacks t he current program counter and the low byte of the processor status register (srl), as shown in figure 8-2 . the low byte of the status register contains the processor priority level at the time prior to the beginning of the interrupt cycle. the processor then loads the priority level for this interrupt into the status register. this action disables all lower priority interrupts until the completion of the interrupt service routine (isr). figure 8-2: interrupt stack frame the retfie (return from interrupt ) instruction unstacks the program counter and status registers to return the processor to its state prior to the interrupt sequence. 8.5 alternate vector table in program memory, the interrupt vector table (ivt) is followed by the alternate interrupt vector table (aivt), as shown in figure 8-1 . access to the alternate vector table is provided by the altivt bit in the intcon2 register. if the altivt bit is set, all interrupt and exception processes use the alternate vect ors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not required, the program memory allocated to the aivt may be used for other purposes. aivt is not a protected section and may be freely programmed by the user. address error trap vector oscillator fail trap vector stack error trap vector reserved vector math error trap vector reserved oscillator fail trap vector address error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ? ? ? interrupt 52 vector interrupt 53 vector math error trap vector decreasing priority 0x000000 0x000014 reserved stack error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ? ? ? interrupt 52 vector interrupt 53 vector ivt aivt 0x000080 0x00007e 0x0000fe reserved 0x000094 reset - goto instruction reset - goto address 0x000002 reserved 0x000082 0x000084 0x000004 reserved vector note 1: the user can always lower the priority level by writing a new value into sr. the interrupt service routine must clear the interrupt flag bits in the ifsx register before lowering the processor interrupt priority, in order to avoid recursive interrupts. 2: the ipl3 bit (corcon<3>) is always clear when interrupts are being processed. it is set only during execution of traps. dspic30f2011/2012/3012/3013 ds70139g-page 70 ? 2010 microchip technology inc. 8.6 fast context saving a context saving option is available using shadow registers. shadow registers are provided for the dc, n, ov, z and c bits in sr, and the registers w0 through w3. the shadows are only one level deep. the shadow registers are accessible using the push.s and pop.s instructions only. when the processor vectors to an interrupt, the push.s instruction can be used to store the current value of the aforementioned registers into their respective shadow registers. if an isr of a certain priority uses the push.s and pop.s instructions for fast context saving, then a higher priority isr should not include the same instruc- tions. users must save the key registers in software during a lower priority interrupt if the higher priority isr uses fast context saving. 8.7 external interrupt requests the interrupt controller supports three external interrupt request signals, int0-int2. these inputs are edge sensitive; they require a low-to-high or a high-to-low transition to generate an interrupt request. the intcon2 register has three bits, int0ep-int2ep, that select the polarity of the edge detection circuitry. 8.8 wake-up from sleep and idle the interrupt controller ma y be used to wake-up the processor from either sleep or idle modes, if sleep or idle mode is active when the interrupt is generated. if an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. at the same time, the processor wakes up from sleep or idle and begins execution of the isr needed to process the interrupt request. ? 2010 microchip technology inc. ds70139g-page 71 dspic30f2011/2012/3012/3013 table 8-2: dspic30f2011 /2012/3012 interrupt controller register map sfr name adr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state intcon1 0080 nstdis ? ? ? ? ovate ovbte covte ? ? ? matherr addrerr stkerr oscfail ? 0000 0000 0000 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 0000 0000 0000 ifs0 0084 cnif mi2cif si2cif nvmif adif u1txif u1rxif spi1if t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 0000 0000 0000 ifs1 0086 ? ? ? ? ? ? ? ?int2if ? ? ? ? ? ?int1if 0000 0000 0000 0000 ifs2 0088 ? ? ? ? ?lvdif ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 iec0 008c cnie mi2cie si2cie nvmie adie u1txie u1rxie spi1ie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 0000 0000 0000 iec1 008e ? ? ? ? ? ? ? ?int2ie ? ? ? ? ? ?int1ie 0000 0000 0000 0000 iec2 0090 ? ? ? ? ?lvdie ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc0 0094 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 0100 0100 0100 0100 ipc1 0096 ? t31p<2:0> ? t2ip<2:0> ? oc2ip<2:0> ?ic2ip<2:0> 0100 0100 0100 0100 ipc2 0098 ?adip<2:0> ? u1txip<2:0> ? u1rxip<2:0> ? spi1ip<2:0> 0100 0100 0100 0100 ipc3 009a ? cnip<2:0> ?mi2cip<2:0> ? si2cip<2:0> ?nvmip<2:0> 0100 0100 0100 0100 ipc4 009c ? ? ? ? ? ? ? ? ? ? ? ? ? int1ip<2:0> 0000 0000 0000 0100 ipc5 009e ? int2ip<2:0> ? ? ? ? ? ? ? ? ? ? ? ? 0100 0000 0000 0000 ipc6 00a0 ? ? ? ? ? ? ? ? ?10 0 ?100 0000 0000 0100 0100 ipc7 00a2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc8 00a4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc9 00a6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc10 00a8 ? ? ? ? ?lvdip<2:0> ? ? ? ? ? ? ? ? 0000 0100 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 72 ? 2010 microchip technology inc. table 8-3: dspic30f3013 interr upt controller register map sfr name adr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state intcon1 0080 nstdis ? ? ? ? ovate ovbte covte ? ? ? matherr addrerr stkerr oscfail ? 0000 0000 0000 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 0000 0000 0000 ifs0 0084 cnif mi2cif si2cif nvmif adif u1txif u1rxif spi1if t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 0000 0000 0000 ifs1 0086 ? ? ? ? ? ? u2txif u2rxif int2if ? ? ? ? ? ?int1if 0000 0000 0000 0000 ifs2 0088 ? ? ? ? ?lvdif ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 iec0 008c cnie mi2cie si2cie nvmie adie u1txie u1rxie spi1ie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 0000 0000 0000 iec1 008e ? ? ? ? ? u2txie u2rxie int2ie ? ? ? ? ? ?int1ie 0000 0000 0000 0000 iec2 0090 ? ? ? ? ?lvdie ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc0 0094 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 0100 0100 0100 0100 ipc1 0096 ? t31p<2:0> ? t2ip<2:0> ? oc2ip<2:0> ?ic2ip<2:0> 0100 0100 0100 0100 ipc2 0098 ?adip<2:0> ? u1txip<2:0> ? u1rxip<2:0> ? spi1ip<2:0> 0100 0100 0100 0100 ipc3 009a ? cnip<2:0> ?mi2cip<2:0> ? si2cip<2:0> ?nvmip<2:0> 0100 0100 0100 0100 ipc4 009c ? ? ? ? ? ? ? ? ? ? ? ? ? int1ip<2:0> 0000 0000 0000 0100 ipc5 009e ? int2ip<2:0> ? ? ? ? ? ? ? ? ? 0100 0000 0000 0000 ipc6 00a0 ? ? ? ? ? ? ? ? ? u2txip<2:0> ? u2rxip<2:0> 0000 0000 0100 0100 ipc7 00a2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc8 00a4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc9 00a6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 0000 0000 ipc10 00a8 ? ? ? ? ?lvdip<2:0> ? ? ? ? ? ? ? ? 0000 0100 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. ? 2010 microchip technology inc. ds70139g-page 73 dspic30f2011/2012/3012/3013 9.0 timer1 module this section describes the 16-bit general purpose timer1 module and associated operational modes. figure 9-1 depicts the simplified block diagram of the 16-bit timer1 module. the following sections provide detailed descriptions including setup and control registers, along with associated block diagrams for the operational modes of the timers. the timer1 module is a 16-bit timer that serves as the time counter for the real-time clock or operates as a free-running interval timer/counter. the 16-bit timer has the following modes: ? 16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter these operational characteristics are supported: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal these operating modes are de termined by setting the appropriate bit(s) in the 16-bit sfr, t1con. figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit timer mode: in the 16-bit ti mer mode, the timer increments on every instruction cycle up to a match value preloaded into the period register pr1, then resets to ? 0 ? and continues to count. when the cpu goes into the idle mode, the timer stops incrementing unless the tsidl (t1con<13>) bit = 0 . if tsidl = 1 , the timer module logic resumes the incre- menting sequence on termination of cpu idle mode. 16-bit synchronous counter mode: in the 16-bit synchronous counter mode, the timer increments on the rising edge of the applied external clock signal which is synchronized with th e internal phase clocks. the timer counts up to a match value preloaded in pr1, then resets to ? 0 ? and continues. when the cpu goes into the idle mode, the timer stops incrementing unless the respective tsidl bit = 0 . if tsidl = 1 , the timer module logic resumes the incrementing sequence upon termination of the cpu idle mode. 16-bit asynchronous counter mode: in the 16-bit asynchronous counter mode, the timer increments on every rising edge of the applied external clock signal. the timer counts up to a match value preloaded in pr1, then resets to ? 0 ? and continues. when the timer is configured for the asynchronous mode of operation and th e cpu goes into the idle mode, the timer stops in crementing if tsidl = 1 . figure 9-1: 16-bit time r1 module block diagram note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual ? (ds70046). ton sync sosci sosco/ pr1 t1if equal comparator x 16 tmr1 reset lposcen event flag 1 0 tsync q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1 x 0 1 tgate 0 0 gate sync dspic30f2011/2012/3012/3013 ds70139g-page 74 ? 2010 microchip technology inc. 9.1 timer gate operation the 16-bit timer can be placed in the gated time accumulation mode. this mode allows the internal t cy to increment the respective timer when the gate input signal (t1ck pin) is asserted high. control bit, tgate (t1con<6>), must be set to enable this mode. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). when the cpu goes into idle mode, the timer stops incrementing unless tsidl = 0 . if tsidl = 1 , the timer resumes the incrementing sequence upon termination of the cpu idle mode. 9.2 timer prescaler the input clock (f osc /4 or external cl ock) to the 16-bit timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits , tckps<1:0> (t1con<5:4>). the prescaler counter is cleared when any of the following occurs: ? a write to the tmr1 register ? a write to the t1con register ? a device reset, such as a por and bor however, if the timer is disabled (ton = 0 ), then the timer prescaler cannot be reset since the prescaler clock is halted. the tmr1 register is not cleared when the t1con register is written. it is cleared by writing to the tmr1 register. 9.3 timer operation during sleep mode the timer operates during cpu sleep mode, if: ? the timer module is enabled (ton = 1 ), and ? the timer clock source is selected as external (tcs = 1 ), and ? the tsync bit (t1con<2>) is asserted to a logic ? 0 ? which defines the external clock source as asynchronous. when all three conditions are true, the timer continues to count up to the period register and be reset to 0x0000. when a match between the timer and the period register occurs, an interr upt can be generated if the respective timer interrupt enable bit is asserted. 9.4 timer interrupt the 16-bit timer has the ability to generate an interrupt-on-period match. when the timer count matches the period register, t he t1if bit is asserted and an interrupt is generated, if enabled. the t1if bit must be cleared in software. the timer interrupt flag, t1if, is located in the ifs0 control register in the interrupt controller. when the gated time accumulation mode is enabled, an interrupt is also generated on the falling edge of the gate signal (at the end of the accumulation cycle). enabling an interrupt is accomplished via the respective timer interrupt enable bit, t1ie. the timer interrupt enable bit is located in the iec0 control register in the interrupt controller. 9.5 real-time clock timer1, when operating in real-time clock (rtc) mode, provides time of day and event time-stamping capabilities. key operational features of the rtc are: ? operation from 32 khz lp oscillator ? 8-bit prescaler ? low power ? real-time clock interrupts these operating modes are determined by setting the appropriate bit(s) in the t1con register. figure 9-2: recommended components for timer1 lp oscillator rtc 9.5.1 rtc oscillator operation when the ton = 1 , tcs = 1 and tgate = 0 , the timer increments on the rising edge of the 32 khz lp oscilla- tor output signal, up to the value specified in the period register and is then reset to ? 0 ?. the tsync bit must be asserted to a logic ? 0 ? (asynchronous mode) for correct operation. enabling the lposcen bit (osccon<1>) disables the normal timer and counter modes and enables a timer carry-out wake-up event. when the cpu enters sleep mode, the rtc continues to operate, provided the 32 khz external crystal oscillator is active and the control bits have not been changed. the tsidl bit should be cleared to ? 0 ? in order for rtc to continue operation in idle mode. 9.5.2 rtc interrupts when an interrupt event occurs, the respective interrupt flag, t1if, is asserted and an interrupt is generated if enabled. the t1if bit must be cleared in software. the respective timer in terrupt flag, t1if, is located in the ifs0 register in th e interrupt controller. sosci sosco r c1 c2 dspic30fxxxx 32.768 khz xtal c1 = c2 = 18 pf; r = 100k ? 2010 microchip technology inc. ds70139g-page 75 dspic30f2011/2012/3012/3013 enabling an interrupt is accomplished via the respective timer interrupt enable bit, t1ie. the timer interrupt enable bit is located in the iec0 control register in the interrupt controller. dspic30f2011/2012/3012/3013 ds70139g-page 76 ? 2010 microchip technology inc. table 9-1: timer1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state tmr1 0100 timer1 register uuuu uuuu uuuu uuuu pr1 0102 period register 1 1111 1111 1111 1111 t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. ? 2010 microchip technology inc. ds70139g-page 77 dspic30f2011/2012/3012/3013 10.0 timer2/3 module this section describes the 32-bit general purpose timer module (timer2/3) and associated operational modes. figure 10-1 depicts the simplified block diagram of the 32-bit timer2/3 module. figure 10-2 and figure 10-3 show timer2/3 configured as two independent 16-bit timers, timer2 and timer3, respectively. the timer2/3 module is a 32-bit timer (which can be configured as two 16-bit timers) with selectable operating modes. these timers are utilized by other peripheral modules, such as: ? input capture ? output compare/simple pwm the following sections provide a detailed description, including setup and control registers, along with associated block diagrams for the operational modes of the timers. the 32-bit timer has the following modes: ? two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer operation ? single 32-bit synchronous counter further, the following operational characteristics are supported: ? adc event trigger ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match these operating modes are determined by setting the appropriate bit(s) in the 16-bit t2con and t3con sfrs. for 32-bit timer/counter operat ion, timer2 is the ls word and timer3 is the ms word of the 32-bit timer. 16-bit timer mode: in the 16-bit mode, timer2 and timer3 can be configured as two independent 16-bit timers. each timer can be set up in either 16-bit timer mode or 16-bit synchronous counter mode. see section 9.0 ?timer1 module? for details on these two operating modes. the only functional difference between timer2 and timer3 is that timer2 prov ides synchronization of the clock prescaler output. this is useful for high frequency external clock inputs. 32-bit timer mode: in the 32-bit ti mer mode, the timer increments on every instruction cycle, up to a match value preloaded into the combined 32-bit period register pr3/pr2, then resets to ? 0 ? and continues to count. for synchronous 32-bit re ads of the timer2/timer3 pair, reading the ls word (tmr2 register) causes the ms word to be read and latched into a 16-bit holding register, termed tmr3hld. for synchronous 32-bit wr ites, the holding register (tmr3hld) must first be written to. when followed by a write to the tmr2 register , the contents of tmr3hld is transferred and latched into the msb of the 32-bit timer (tmr3). 32-bit synchronous counter mode: in the 32-bit synchronous counter mode, the timer increments on the rising edge of the applied external clock signal which is synchronized with th e internal phase clocks. the timer counts up to a match value preloaded in the combined 32-bit period register, pr3/pr2, then resets to ? 0 ? and continues. when the timer is configured for the synchronous counter mode of operation and the cpu goes into the idle mode, the timer stops incrementing unless the tsidl bit (t2con<13>) = 0 . if tsidl = 1 , the timer module logic resumes the incrementing sequence upon termination of the cpu idle mode. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual ?(ds70046). note: for 32-bit timer operation, t3con control bits are ignored. only t2con control bits are used for setup and control. timer2 clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is generated with the timer3 interrupt flag (t3if) and the interrupt is enabled with the timer3 interrupt enable bit (t3ie). dspic30f2011/2012/3012/3013 ds70139g-page 78 ? 2010 microchip technology inc. figure 10-1: 32-bit timer2/3 block diagram tmr3 tmr2 t3if equal comparator x 32 pr3 pr2 reset lsb msb event flag note: timer configuration bit t32 (t2con<3>) must be set to ? 1 ? for a 32-bit timer/counter operation. all control bits are respective to the t2con register. data bus<15:0> read tmr2 write tmr2 16 16 16 q qd ck tgate (t2con<6>) (t2con<6>) tgate 0 1 ton tckps<1:0> 2 t cy tcs 1 x 0 1 tgate 0 0 gate t2ck sync adc event trigger sync tmr3hld prescaler 1, 8, 64, 256 ? 2010 microchip technology inc. ds70139g-page 79 dspic30f2011/2012/3012/3013 figure 10-2: 16-bit timer2 block diagram figure 10-3: 16-bit timer3 block diagram ton sync pr2 t2if equal comparator x 16 tmr2 reset event flag tgate tckps<1:0> 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 gate t2ck sync prescaler 1, 8, 64, 256 q qd ck ton pr3 t3if equal comparator x 16 tmr3 reset event flag tgate tckps<1:0> 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 t3ck adc event trigger sync q q d ck prescaler 1, 8, 64, 256 dspic30f2011/2012/3012/3013 ds70139g-page 80 ? 2010 microchip technology inc. 10.1 timer gate operation the 32-bit timer can be placed in the gated time accumulation mode. this mode allows the internal t cy to increment the respective timer when the gate input signal (t2ck pin) is asserted high. control bit, tgate (t2con<6>), must be set to enable this mode. when in this mode, timer2 is the originating clock source. the tgate setting is ignored for timer3. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). the falling edge of the external signal terminates the count operation but does not reset the timer. the user must reset the timer in order to start counting from zero. 10.2 adc event trigger when a match occurs between the 32-bit timer (tmr3/tmr2) and the 32-bit combined period register (pr3/pr2), or between the 16-bit timer tmr3 and the 16-bit period register pr3, a special adc trigger event signal is generated by timer3. 10.3 timer prescaler the input clock (f osc /4 or external cl ock) to the timer has a prescale option of 1: 1, 1:8, 1:64, and 1:256, selected by control bits, tckps<1:0> (t2con<5:4> and t3con<5:4>). for the 32-bit timer operation, the originating clock source is timer2. the prescaler operation for timer3 is not applicable in this mode. the prescaler counter is cleared when any of the following occurs: ? a write to the tmr2/tmr3 register ? a write to the t2con/t3con register ? a device reset, such as a por and bor however, if the timer is disabled (ton = 0 ), the timer 2 prescaler cannot be reset since the prescaler clock is halted. tmr2/tmr3 is not clear ed when t2con/t3con is written. 10.4 timer operation during sleep mode the timer does not operate during cpu sleep mode because the internal clocks are disabled. 10.5 timer interrupt the 32-bit timer module can generate an interrupt-on-period match or on the falling edge of the external gate signal. when the 32-bit timer count matches the respective 32-bit period register, or the falling edge of the external ?gat e? signal is detected, the t3if bit (ifs0<7>) is asserted and an interrupt is generated if enabled. in th is mode, the t3if interrupt flag is used as the source of the interrupt. the t3if bit must be cleared in software. enabling an interrupt is accomplished via the respective timer interrupt ena ble bit, t3ie (iec0<7>). ? 2010 microchip technology inc. ds70139g-page 81 dspic30f2011/2012/3012/3013 table 10-1: timer2/3 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state tmr2 0106 timer2 register uuuu uuuu uuuu uuuu tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu tmr3 010a timer3 register uuuu uuuu uuuu uuuu pr2 010c period register 2 1111 1111 1111 1111 pr3 010e period register 3 1111 1111 1111 1111 t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 0000 0000 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 82 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 83 dspic30f2011/2012/3012/3013 11.0 input capture module this section describes the input capture module and associated operational modes. the features provided by this module are useful in applications requiring frequency (period) and pulse measurement. figure 11-1 depicts a block diagram of the input capture module. input capture is useful for such modes as: ? frequency/period/pulse measurements ? additional sources of external interrupts important operational featur es of the input capture module are: ? simple capture event mode ? timer2 and timer3 mode selection ? interrupt on input capture event these operating modes are determined by setting the appropriate bits in the ic1con and ic2con registers. the dspic30f2011/2012/3012/3013 devices have two capture channels. 11.1 simple capture event mode the simple capture events in the dspic30f product family are: ? capture every falling edge ? capture every rising edge ? capture every 4th rising edge ? capture every 16th rising edge ? capture every rising and falling edge these simple input capture modes are configured by setting the appropriate bits, icm<2:0> (icxcon<2:0>). 11.1.1 capture prescaler there are four input capture prescaler settings specified by bits icm<2:0> (icxcon<2:0>). whenever the capture channel is turned off, the prescaler counter is cleared. in addition, any reset clears the prescaler counter. figure 11-1: input capture mode block diagram (1) note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). icxbuf prescaler icx pin icm<2:0> mode select 3 note 1: where ?x? is shown, reference is m ade to the registers or bits associated to the respective input capture channel (1 or 2). 10 set flag icxif ictmr t2_cnt t3_cnt edge detection logic clock synchronizer 1, 4, 16 from gp timer module 16 16 fifo r/w logic ici<1:0> icbne, icov icxcon interrupt logic set flag icxif data bus dspic30f2011/2012/3012/3013 ds70139g-page 84 ? 2010 microchip technology inc. 11.1.2 capture buffer operation each capture channel has an associated fifo buffer which is four 16-bit word s deep. there are two status flags which provide status on the fifo buffer: ? icbne ? input capture buffer not empty ? icov ? input capture overflow the icbne is set on the first input capture event and remains set until all capture events have been read from the fifo. as each word is read from the fifo, the remaining words are advanced by one position within the buffer. in the event that the fifo is full with four capture events, and a fifth capture event occurs prior to a read of the fifo, an overflow condition occurs and the icov bit is set to a logic ? 1 ?. the fifth capture event is lost and is not stored in the fifo. no additional events are captured until all four events have been read from the buffer. if a fifo read is performe d after the last read and no new capture event has been received, the read will yield indeterminate results. 11.1.3 timer2 and timer3 selection mode the input capture module consists of up to 8 input capture channels. each channel can select between one of two timers for the ti me base, timer2 or timer3. selection of the timer resource is accomplished through sfr bit, ictmr (icxcon<7>). timer3 is the default timer resource available for the input capture module. 11.1.4 hall sensor mode when the input capture module is set for capture on every edge, rising and falling, icm<2:0> = 001 , the following operations are performed by the input capture logic: ? the input capture interrupt flag is set on every edge, rising and falling. ? the interrupt on capture mode setting bits, ici<1:0>, is ignored since every capture generates an interrupt. ? a capture overflow condition is not generated in this mode. 11.2 input capture operation during sleep and idle modes an input capture event generates a device wake-up or interrupt, if enabled, if the device is in cpu idle or sleep mode. independent of the timer being enabled, the input capture module wakes up from the cpu sleep or idle mode when a capture event occurs if icm<2:0> = 111 and the interrupt enable bit is asserted. the same wake-up can generate an interrupt if the conditions for processing the interrupt have been satisfied. the wake-up feature is useful as a method of adding extra external pin interrupts. 11.2.1 input capture in cpu sleep mode cpu sleep mode allows input capture module operation with reduced func tionality. in the cpu sleep mode, the ici<1:0> bits are not applicable and the input capture module can only function as an external interrupt source. the capture module must be configured for interrupt only on rising edge (icm<2:0> = 111 ) in order for the input capture module to be used while the device is in sleep mode. the prescale sett ings of 4:1 or 16:1 are not applicable in this mode. 11.2.2 input capture in cpu idle mode cpu idle mode allows inpu t capture module operation with full functionality. in the cpu idle mode, the interrupt mode selected by the ici<1:0> bits is applicable, as well as the 4:1 and 16:1 capture prescale settings which are defined by control bits icm<2:0>. this mode requires the selected timer to be enabled. moreover, the icsidl bit must be asserted to a logic ? 0 ?. if the input capture module is defined as icm<2:0> = 111 in cpu idle mode, the input capture pin serves only as an external interrupt pin. 11.3 input capture interrupts the input capture channels have the ability to generate an interrupt based on the se lected number of capture events. the selection number is set by control bits, ici<1:0> (icxcon<6:5>). each channel provides an interrupt flag (icxif) bit. the respective capture channel interrupt flag is located in the corresponding ifsx register. enabling an interrupt is accomplished via the respective capture channel interrupt enable (icxie) bit. the capture interrupt enable bit is located in the corresponding iec control register. ? 2010 microchip technology inc. ds70139g-page 85 dspic30f2011/2012/3012/3013 table 11-1: input capture register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state ic1buf 0140 input 1 capture register uuuu uuuu uuuu uuuu ic1con 0142 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic2buf 0144 input 2 capture register uuuu uuuu uuuu uuuu ic2con 0146 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 86 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 87 dspic30f2011/2012/3012/3013 12.0 output compare module this section describes the output compare module and associated operational modes. the features provided by this module are useful in applications requiring operational modes, such as: ? generation of variable width output pulses ? power factor correction figure 12-1 depicts a block diagram of the output compare module. the key operational features of the output compare module include: ? timer2 and timer3 selection mode ? simple output compare match mode ? dual output compare match mode ? simple pwm mode ? output compare during sleep and idle modes ? interrupt on output compare/pwm event these operating modes are determined by setting the appropriate bits in the 16-bit oc1con and oc2con registers. the dspic30f2011/2012/3012/3013 devices have 2 compare channels. ocxrs and ocxr in figure 12-1 represent the dual compare registers. in the dual compare mode, the ocxr register is used for the first compare and ocxrs is used for the second compare. figure 12-1: output compare mode block diagram (1) note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). ocxr comparator output logic q s r ocm<2:0> output ocx set flag bit ocxif ocxrs mode select 3 note 1: where ?x? is shown, reference is made to the regist ers associated with the respective output compare channel (1 or 2). ocfa octsel 01 t2p2_match tmr2<15:0 tmr3<15:0> t3p3_match from gp (for x = 1, 2, 3 or 4) 01 timer module enable dspic30f2011/2012/3012/3013 ds70139g-page 88 ? 2010 microchip technology inc. 12.1 timer2 and timer3 selection mode each output compare channel can select between one of two 16-bit timers, timer2 or timer3. the selection of the timers is controlled by the octsel bit (ocxcon<3>). timer2 is the default timer resource for the output compare module. 12.2 simple output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 001 , 010 or 011 , the selected output compare channel is configured for one of three simple output compare match modes: ? compare forces i/o pin low ? compare forces i/o pin high ? compare toggles i/o pin the ocxr register is used in these modes. the ocxr register is loaded with a value and is compared to the selected incrementing timer count. when a compare occurs, one of these compare match modes occurs. if the counter resets to zero before reaching the value in ocxr, the state of the ocx pin remains unchanged. 12.3 dual output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 100 or 101 , the selected output compare channel is configured for one of two dual output compare modes, which are: ? single output pulse mode ? continuous output pulse mode 12.3.1 single pulse mode for the user to configure the module for the generation of a single output pulse, the following steps are required (assuming timer is off): ? determine instruction cycle time t cy . ? calculate desired pulse width value based on t cy . ? calculate time to start pul se from timer start value of 0x0000. ? write pulse width start and stop times into ocxr and ocxrs compare registers (x denotes channel 1 to n). ? set timer period register to value equal to or greater than value in ocxrs compare register. ? set ocm<2:0> = 100 . ? enable timer, ton bit (txcon<15>) = 1 . to initiate another single pulse, issue another write to set ocm<2:0> = 100 . 12.3.2 continuous pulse mode for the user to configure the module for the generation of a continuous stream of ou tput pulses, the following steps are required: ? determine instruction cycle time t cy . ? calculate desired pulse value based on t cy . ? calculate timer to start pu lse width from timer start value of 0x0000. ? write pulse width start and stop times into ocxr and ocxrs (x denotes channel 1 to n) compare registers, respectively. ? set timer period register to value equal to or greater than value in ocxrs compare register. ? set ocm<2:0> = 101 . ? enable timer, ton bit (txcon<15>) = 1 . 12.4 simple pwm mode when control bits ocm<2:0> (ocxcon<2:0>) = 110 or 111 , the selected output compare channel is configured for the pwm mo de of operation. when configured for the pwm mode of operation, ocxr is the main latch (read-only) and ocxrs is the secondary latch. this enables glitchless pwm transitions. the user must perform the following steps in order to configure the output compare module for pwm operation: 1. set the pwm period by writing to the appropriate period register. 2. set the pwm duty cycle by writing to the ocxrs register. 3. configure the output compare module for pwm operation. 4. set the tmrx prescale value and enable the timer, ton bit (txcon<15>) = 1 . 12.4.1 input pin fault protection for pwm when control bits ocm<2:0> (ocxcon<2:0>) = 111 , the selected output co mpare channel is again configured for the pwm mode of operation with the additional feature of input fault protection. while in this mode, if a logic ? 0 ? is detected on the ocfa/b pin, the respective pwm output pin is placed in the high impedance input state. th e ocflt bit (ocxcon<4>) indicates whether a fault condition has occurred. this state is maintained until both of the following events have occurred: ? the external fault condition has been removed. ? the pwm mode has been re-enabled by writing to the appropriate control bits. ? 2010 microchip technology inc. ds70139g-page 89 dspic30f2011/2012/3012/3013 12.4.2 pwm period the pwm period is specified by writing to the prx register. the pwm period can be calculated using equation 12-1 . equation 12-1: pwm frequency is defined as 1/[pwm period]. when the selected tmrx is equal to its respective period register, prx, the following four events occur on the next increment cycle: ? tmrx is cleared. ? the ocx pin is set. - exception 1: if pwm duty cycle is 0x0000, the ocx pin remains low. - exception 2: if duty cycl e is greater than prx, the pin remains high. ? the pwm duty cycle is latched from ocxrs into ocxr. ? the corresponding timer interrupt flag is set. see figure 12-2 for key pwm period comparisons. timer3 is referred to in figure 12-2 for clarity. figure 12-2: pwm output timing pwm period = [(prx) + 1] ? 4 ? tosc ? (tmrx prescale value) period duty cycle tmr3 = duty cycle tmr3 = duty cycle tmr3 = pr3 t3if = 1 (interrupt flag) ocxr = ocxrs tmr3 = pr3 (interrupt flag) ocxr = ocxrs t3if = 1 (ocxr) (ocxr) dspic30f2011/2012/3012/3013 ds70139g-page 90 ? 2010 microchip technology inc. 12.5 output compare operation during cpu sleep mode when the cpu enters sleep mode, all internal clocks are stopped. therefore, when the cpu enters the sleep state, the output comp are channel drives the pin to the active state that was observed prior to entering the cpu sleep state. for example, if the pin was high when the cpu entered the sleep state, the pin remains high. likewise, if the pin was low when the cpu entered the sleep state, the pin remains low. in either case, the output compare module resumes operation when the device wakes up. 12.6 output compare operation during cpu idle mode when the cpu enters th e idle mode, the output compare module can oper ate with full functionality. the output compare channel operates during the cpu idle mode if the ocsidl bi t (ocxcon<13>) is at logic ? 0 ? and the selected time base (timer2 or timer3) is enabled and the tsidl bit of the selected timer is set to logic ? 0 ?. 12.7 output compare interrupts the output compare channels have the ability to generate an interrupt on a compare match, for whichever match mode has been selected. for all modes except the pwm mode, when a compare event occurs, the respective interrupt flag (ocxif) is asserted and an interrupt is generated if enabled. the ocxif bit is located in the corresponding ifs register and must be cleared in software. the interrupt is enabled via the respective compare interrupt enable (ocxie) bit located in the corresponding iec control register. for the pwm mode, when an event occurs, the respective timer interrupt flag (t2if or t3if) is asserted and an interrupt is generat ed if enabled. the if bit is located in the ifs0 register and must be cleared in software. the interrupt is enabled via the respective timer interrupt enable bit (t2ie or t3ie) located in the iec0 control register. t he output compare interrupt flag is never set during the pwm mode of operation. ? 2010 microchip technology inc. ds70139g-page 91 dspic30f2011/2012/3012/3013 table 12-1: output compare register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state oc1rs 0180 output compare 1 secondary register 0000 0000 0000 0000 oc1r 0182 output compare 1 main register 0000 0000 0000 0000 oc1con 0184 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc2rs 0186 output compare 2 secondary register 0000 0000 0000 0000 oc2r 0188 output compare 2 main register 0000 0000 0000 0000 oc2con 018a ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 92 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 93 dspic30f2011/2012/3012/3013 13.0 spi? module the serial peripheral interface (spi?) module is a synchronous serial interface. it is useful for communicating with other peripheral devices, such as eeproms, shift registers, display drivers and a/d converters, or other microcontrollers. it is compatible with motorola's spi and siop interfaces. the dspic30f2011/2012/3012/3013 devices feature one spi module, spi1. 13.1 operating function description figure 13-1 is a simplified block diagram of the spi module, which consists of a 16-bit shift register, spi1sr, used for shifting data in and out, and a buffer register, spi1buf. control register spi1con (not shown) configures the module. additionally, status register spi1stat (not shown) indicates various status conditions. four i/o pins comprise the serial interface: ? sdi1 (serial data input) ? sdo1 (serial data output) ? sck1 (shift clock input or output) ? ss1 (active-low slave select). in master mode operation, sck1 is a clock output. in slave mode, it is a clock input. a series of eight (8) or sixteen (16) clock pulses shift out bits from the spi1sr to sdo1 pin and simultaneously shift in data from sdi1 pin. an interrupt is generated when the transfer is complete and the interrupt flag bit (spi1if) is set. this interrupt can be disabled through the interrupt enable bit, spi1ie. the receive operation is double-buffered. when a complete byte is received, it is transferred from spi1sr to spi1buf. if the receive buffer is full when new data is being transferred from spi1sr to spi1buf, the module will set the spirov bit indicating an overflow condition. the transfer of the data fr om spi1sr to spi1buf is not completed and the new data is lost. the module will not respond to scl transitions while spirov is ? 1 ?, effec- tively disabling the module until spi1buf is read by user software. transmit writes are also double-buffered. the user writes to spi1buf. when the master or slave transfer is completed, the conten ts of the shift register (spi1sr) are moved to the receive buffer. if any transmit data has been written to the buffer register, the contents of the transmit bu ffer are moved to spi1sr. the received data is thus placed in spi1buf and the transmit data in spi1sr is ready for the next transfer. note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual ? (ds70046). note: see ? dspic30f family reference manual? (ds70046) for detailed information on the control and status registers. note: both the transmit buffer (spi1txb) and the receive buffer (spi1rxb) are mapped to the same register address, spi1buf. dspic30f2011/2012/3012/3013 ds70139g-page 94 ? 2010 microchip technology inc. figure 13-1: spi block diagram figure 13-2 depicts the a master/slave connection between two processors. in master mode, the clock is generated by prescaling t he system clock. data is transmitted as soon as a value is written to spi1buf. the interrupt is generated at the middle of the transfer of the last bit. in slave mode, data is transmitted and received as external clock pulses appear on sck. again, the interrupt is generated when the last bit is latched. if ss 1 control is enabled, then transmission and reception are enabled only when ss 1 = low. the sdo1 output will be disabled in ss 1 mode with ss 1 high. the clock provided to the module is (f osc /4). this clock is then prescaled by the primary (ppre<1:0>) and the secondary (spre<2:0>) prescale factors. the cke bit determines whether transmit occurs on transition from active clock state to idle clock state, or vice versa. the ckp bit selects the idle state (high or low) for the clock. 13.1.1 word and byte communication a control bit, mode 16 (spi1con<10>), allows the module to communicate in ei ther 16-bit or 8-bit mode. 16-bit operation is identica l to 8-bit operation except that the number of bits tran smitted is 16 instead of 8. the user software must disable the module prior to changing the mode16 bit. the spi module is reset when the mode16 bit is changed by the user. a basic difference between 8- bit and 16-bit operation is that the data is transmitted out of bit 7 of the spi1sr for 8-bit operation, and data is transmitted out of bit 15 of the spi1sr for 16-bit operation. in both modes, data is shifted into bit 0 of the spi1sr. 13.1.2 sdo1 disable a control bit, dissdo, is provided to the spi1con register to allow the sdo1 output to be disabled. this will allow the spi module to be connected in an input only configuration. sdo1 can also be used for general purpose i/o. 13.2 framed spi support the module supports a basic framed spi protocol in master or slave mode. the control bit, frmen, enables framed spi support and causes the ss1 pin to perform the frame synchr onization pulse (fsync) function. the control bit, spifsd, determines whether the ss1 pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). the frame pulse is an active-high pulse for a si ngle spi clock cycle. when frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the spi clock. read write internal data bus sdi1 sdo1 ss 1 sck1 spi1sr spixbuf bit 0 shift clock edge select f cy primary 1, 4, 16, 64 enable master clock prescaler secondary prescaler 1:1 ? 1:8 ss & fsync control clock control transmit spixbuf receive ? 2010 microchip technology inc. ds70139g-page 95 dspic30f2011/2012/3012/3013 figure 13-2: spi master/slave connection 13.3 slave select synchronization the ss 1 pin allows a synchronous slave mode. the spi must be configured in spi slave mode with ss 1 pin control enabled (ssen = 1 ). when the ss 1 pin is low, transmission and reception are enabled and the sdox pin is driven. when ss 1 pin goes high, the sdox pin is no longer driven. also, the spi module is resynchronized, and all counters/control circuitry are reset. therefore, when the ss 1 pin is asserted low again, transmission/reception will begin at the msb even if ss 1 had been de-asserted in the middle of a transmit/receive. 13.4 spi operation during cpu sleep mode during sleep mode, the spi module is shut down. if the cpu enters sleep mode while an spi transaction is in progress, then the transmission and reception is aborted. the transmitter and receiver will stop in sleep mode. however, register contents are not affected by entering or exiting sleep mode. 13.5 spi operation during cpu idle mode when the device enters idle mode, all clock sources remain functional. the spisidl bit (spi1stat<13>) selects if the spi module will stop or continue on idle. if spisidl = 0 , the module will continue to operate when the cpu enters idle mode. if spisidl = 1 , the module will stop when the cpu enters idle mode. serial input buffer (spi1buf) shift register (spi1sr) msb lsb sdo1 sdi1 processor 1 sck1 spi master serial input buffer (spi1buf) shift register (spi1sr) lsb msb sdi1 sdo1 processor 2 sck1 spi slave serial clock dspic30f2011/2012/3012/3013 ds70139g-page 96 ? 2010 microchip technology inc. table 13-1: spi1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state spi1stat 0220 spien ? spisidl ? ? ? ? ? ? spirov ? ? ? ?spitbfspirbf 0000 0000 0000 0000 spi1con 0222 ? frmen spifsd ? dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 0000 0000 0000 spi1buf 0224 transmit and receive buffer 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual? (ds70046) for descriptions of register bit fields. ? 2010 microchip technology inc. ds70139g-page 97 dspic30f2011/2012/3012/3013 14.0 i 2 c? module the inter-integrated circuit (i 2 c tm ) module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard, with a 16-bit interface. this module offers the following key features: ?i 2 c interface supporting both master and slave operation. ?i 2 c slave mode supports 7-bit and 10-bit addressing. ?i 2 c master mode supports 7-bit and 10-bit addressing. ?i 2 c port allows bidirectional transfers between master and slaves. ? serial clock synch ronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfe r (sclrel control). ?i 2 c supports multi-master operation; detects bus collision and will arbitrate accordingly. 14.1 operating function description the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7 and 10-bit addressing. thus, the i 2 c module can operate either as a slave or a master on an i 2 c bus. 14.1.1 various i 2 c modes the following types of i 2 c operation are supported: ?i 2 c slave operation with 7-bit addressing ?i 2 c slave operation with 10-bit addressing ?i 2 c master operation with 7- bit or 10-bit addressing see the i 2 c programmer?s model ( figure 14-1 ). 14.1.2 pin configuration in i 2 c mode i 2 c has a 2-pin interface; the scl pin is clock and the sda pin is data. 14.1.3 i 2 c registers i2ccon and i2cstat are control and status registers, respectively. the i2ccon register is readable and writable. the lower 6 bits of i2cstat are read-only. the remaining bits of t he i2cstat are read/write. i2crsr is the shift register used for shifting data, whereas i2crcv is the buff er register to which data bytes are written, or from which data bytes are read. i2crcv is the receive buffer as shown in figure 14-1 . i2ctrn is the transmit re gister to which bytes are written during a transmit operation, as shown in figure 14-2 . the i2cadd register holds the slave address. a status bit, add10, indicates 10-bit address mode. the i2cbrg acts as the baud rate generator reload value. in receive operations, i2crsr and i2crcv together form a double-buffered receiver. when i2crsr receives a complete byte, it is transferred to i2crcv and an interrupt pulse is generated. during transmission, the i2ctrn is not double-buffered. figure 14-1: programmer?s model note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). note: following a restart condition in 10-bit mode, the user only needs to match the first 7-bit address. bit 7 bit 0 i2crcv (8 bits) bit 7 bit 0 i2ctrn (8 bits) bit 8 bit 0 i2cbrg (9 bits) bit 15 bit 0 i2ccon (16 bits) bit 15 bit 0 i2cstat (16 bits) bit 9 bit 0 i2cadd (10 bits) dspic30f2011/2012/3012/3013 ds70139g-page 98 ? 2010 microchip technology inc. figure 14-2: i 2 c? block diagram i2crsr i2crcv internal data bus scl sda shift match detect i2cadd start and stop bit detect clock addr_match clock stretching i2ctrn lsb shift clock write read brg down i2cbrg reload control f cy start, restart, stop bit generate write read acknowledge generation collision detect write read write read i2ccon write read i2cstat control logic read lsb counter ? 2010 microchip technology inc. ds70139g-page 99 dspic30f2011/2012/3012/3013 14.2 i 2 c module addresses the i2cadd register contains the slave mode addresses. the register is a 10-bit register. if the a10m bit (i2ccon<10>) is ? 0 ?, the address is interpreted by the module as a 7-bit address. when an address is received, it is compared to the 7 lsb of the i2cadd register. if the a10m bit is ? 1 ?, the address is assumed to be a 10-bit address. when an address is received, it will be compared with the binary value ? 11110 a9 a8 ? (where a9 and a8 are two most significant bits of i2cadd). if that value matches, the next address will be compared with the least significant 8 bits of i2cadd, as specified in the 10-bit addressing protocol. the 7-bit i 2 c slave addresses supported by the dspic30f are shown in table 14-1 . table 14-1: 7-bit i 2 c? slave addresses 14.3 i 2 c 7-bit slave mode operation once enabled (i2cen = 1 ), the slave module will wait for a start bit to occur (i.e., the i 2 c module is ?idle?). following the detection of a start bit, 8 bits are shifted into i2crsr and the address is compared against i2cadd. in 7-bit mode (a10m = 0 ), bits i2cadd<6:0> are compared against i2crsr<7:1> and i2crsr<0> is the r_w bit. all incoming bits are sampled on the ris- ing edge of scl. if an address match occurs, an acknowledgement will be sent, and the slave event interrupt flag (si2cif) is set on the falling edge of the ninth (ack ) bit. the address match does not affect the contents of the i2crcv buffer or the rbf bit. 14.3.1 slave transmission if the r_w bit received is a ? 1 ?, then the serial port will go into transmit mode. it will send ack on the ninth bit and then hold scl to ? 0 ? until the cpu responds by writing to i2ctrn. scl is released by setting the sclrel bit, and 8 bits of data are shifted out. data bits are shifted out on the falling edge of scl, such that sda is valid during scl high. the interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ack received from the master. 14.3.2 slave reception if the r_w bit received is a ? 0 ? during an address match, then receive mode is initiated. incoming bits are sampled on the rising edge of scl. after 8 bits are received, if i2crcv is not full or i2cov is not set, i2crsr is transferred to i2crcv. ack is sent on the ninth clock. if the rbf flag is set, indicating that i2crcv is still holding data from a previous operation (rbf = 1 ), then ack is not sent; however, the interrupt pulse is generated. in the case of an overflow, the contents of the i2crsr are not loaded into the i2crcv. 14.4 i 2 c 10-bit slave mode operation in 10-bit mode, the basic receive and transmit operations are the same as in the 7-bit mode. however, the criteria for address match is mo re complex. the i 2 c specification dictates that a slave must be addressed for a write operation with two address bytes following a start bit. the a10m bit is a control bit that signifies that the address in i2cadd is a 10-bit address rather than a 7-bit address. the address detection pr otocol for the first byte of a message address is identical for 7-bit and 10-bit messages, but the bits being compared are different. i2cadd holds the entire 10-bit address. upon receiving an address following a start bit, i2crsr <7:3> is compared against a literal ? 11110 ? (the default 10-bit address) and i2crsr<2:1> are compared against i2cadd<9:8>. if a match occurs and if r_w = 0 , the interrupt pulse is sent. the add10 bit will be cleared to indicate a partial address match. if a match fails or r_w = 1 , the add10 bit is cleared and the module returns to the idle state. the low byte of the address is then received and compared with i2cadd<7:0>. if an address match occurs, the interrupt pulse is generated and the add10 bit is set, indicating a complete 10-bit address match. if an address match did not occur, the add10 bit is cleared and the module returns to the idle state. 0x00 general call address or start byte 0x01-0x03 reserved 0x04-0x07 hs-mode master codes 0x04-0x77 valid 7-bit addresses 0x78-0x7b valid 10-bit addresses (lower 7 bits) 0x7c-0x7f reserved note: the i2crcv will be loaded if the i2cov bit = 1 and the rbf flag = 0 . in this case, a read of the i2crcv was performed but the user did not clear the state of the i2cov bit before the next receive occurred. the acknowledgement is not sent (ack = 1 ) and the i2crcv is updated. dspic30f2011/2012/3012/3013 ds70139g-page 100 ? 2010 microchip technology inc. 14.4.1 10-bit mode slave transmission once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as ?prior_addr_match?), the master can begin sending data bytes for a slave reception operation. 14.4.2 10-bit mode slave reception once addressed, the master can generate a repeated start, reset the high byte of the address and set the r_w bit without generating a st op bit, thus initiating a slave transmit operation. 14.5 automatic clock stretch in the slave modes, the m odule can synchronize buffer reads and write to the master device by clock stretching. 14.5.1 transmit clock stretching both 10-bit and 7-bit transmit modes implement clock stretching by asserting the sclrel bit after the falling edge of the ninth clock, if the tbf bit is cleared, indicating the buffer is empty. in slave transmit modes, clock stretching is always performed irrespective of the stren bit. clock synchronization takes place following the ninth clock of the transmit sequence. if the device samples an ack on the falling edge of the ninth clock and if the tbf bit is still clear, then the sclrel bit is automatically cleared. the sclrel being cleared to ? 0 ? will assert the scl line low. the user?s isr must set the sclrel bit before transmission is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the i2ctrn before the master device c an initiate another transmit sequence. 14.5.2 receive clock stretching the stren bit in the i2ccon register can be used to enable clock stretching in slave receive mode. when the stren bit is set, the scl pin will be held low at the end of each data receive sequence. 14.5.3 clock stretching during 7-bit addressing (stren = 1 ) when the stren bit is set in slave receive mode, the scl line is held low when the buffer register is full. the method for stretching the sc l output is the same for both 7 and 10-bit addressing modes. clock stretching takes place following the ninth clock of the receive sequence. on t he falling edge of the ninth clock at the end of the ack sequence, if the rbf bit is set, the sclrel bit is autom atically cleared, forcing the scl output to be held low. the user?s isr must set the sclrel bit before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the i2crcv before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring. 14.5.4 clock stretching during 10-bit addressing (stren = 1 ) clock stretching takes place automatically during the addressing sequence. because this module has a register for the entire addre ss, it is not necessary for the protocol to wait for the address to be updated. after the address phase is complete, clock stretching will occur on each data receive or transmit sequence as was described earlier. 14.6 software controlled clock stretching (stren = 1 ) when the stren bit is ? 1 ?, the sclrel bit may be cleared by software to allow software to control the clock stretching. the logic will synchronize writes to the sclrel bit with the scl clock. clearing the sclrel bit will not assert the scl output until the module detects a falling edge on the scl output and scl is sampled low. if the sclrel bit is cleared by the user while the scl line has been sampled low, the scl output will be asserted (held low). the scl output will remain low until the sclrel bit is set, and all other devices on the i 2 c bus have de-asserted scl. this ensures that a write to the sclrel bit will not violate the minimum high time requirement for scl. if the stren bit is ? 0 ?, a software write to the sclrel bit will be disregarded and have no effect on the sclrel bit. note 1: if the user loads the contents of i2ctrn, setting the tbf bit before the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software, regardless of the state of the tbf bit. note 1: if the user reads the contents of the i2crcv, clearing the rbf bit before the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software regardless of the state of the rbf bit. the user should be careful to clear the rbf bit in the isr before the next receive sequence in order to prevent an overflow condition. ? 2010 microchip technology inc. ds70139g-page 101 dspic30f2011/2012/3012/3013 14.7 interrupts the i 2 c module generates two interrupt flags, mi2cif (i 2 c master interrupt flag) and si2cif (i 2 c slave interrupt flag). the mi2cif interrupt flag is activated on completion of a master message event. the si2cif interrupt flag is activated on detection of a message directed to the slave. 14.8 slope control the i 2 c standard requires slope control on the sda and scl signals for fast mode (400 khz). the control bit, disslw, enables the user to disable slew rate control if desired. it is necessary to disable the slew rate control for 1 mhz mode. 14.9 ipmi support the control bit, ipmien, e nables the module to support intelligent peripheral manage ment interface (ipmi). when this bit is set, the module accepts and acts upon all addresses. 14.10 general call address support the general call address can address all devices. when this address is used, all devices should, in theory, respond with an acknowledgement. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r_w = 0 . the general call address is recognized when the general call enable (gcen) bit is set (i2ccon<7> = 1 ). following a start bit detection, 8 bits are shifted into i2crsr and the address is compared with i2cadd, and is also compared with the general call address which is fixed in hardware. if a general call address match occurs, the i2crsr is transferred to the i2crcv after the eighth clock, the rbf flag is set and on the falling edge of the ninth bit (ack bit), the master event interrupt flag (mi2cif) is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the i2crcv to determine if the address was device specific or a general call address. 14.11 i 2 c master support as a master device, six operations are supported: ? assert a start condition on sda and scl. ? assert a restart condition on sda and scl. ? write to the i2ctrn register initiating transmission of data/address. ? generate a stop condition on sda and scl. ? configure the i 2 c port to receive data. ? generate an ack condition at the end of a received byte of data. 14.12 i 2 c master operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeate d start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case, the data direction bit (r_w) is logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmitted, an ack bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. in this case, the data direction bit (r_w) is logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address, followed by a ? 1 ? to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an ack bit is transmitted. start and stop conditions indicate the beginning and end of transmission. 14.12.1 i 2 c master transmission transmission of a data byte, a 7-bit address, or the sec- ond half of a 10-bit address, is accomplished by simply writing a value to i2ctrn register. the user should only write to i2ctrn when the module is in a wait state. this action will set the buffer full flag (tbf) and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. the transmit status flag, trstat (i2cstat<14>), indicates that a master transmit is in progress. dspic30f2011/2012/3012/3013 ds70139g-page 102 ? 2010 microchip technology inc. 14.12.2 i 2 c master reception master mode reception is enabled by programming the receive enable bit, rcen (i2ccon<3>). the i 2 c module must be idle before the rcen bit is set, otherwise the rcen bit will be disregarded. the baud rate generator begins counting and on each rollover, the state of the scl pin ack and data are shifted into the i2crsr on the rising edge of each clock. 14.12.3 baud rate generator in i 2 c master mode, the reload value for the brg is located in the i2cbrg register. when the brg is loaded with this value, the brg counts down to ? 0 ? and stops until another reload has taken place. if clock arbitration is taking place, for instance, the brg is reloaded when the scl pin is sampled high. as per the i 2 c standard, fsck may be 100 khz or 400 khz. however, the user can specify any baud rate up to 1 mhz. i2cbrg values of ? 0 ? or ? 1 ? are illegal. equation 14-1: serial clock rate 14.12.4 clock arbitration clock arbitration occurs when the master de-asserts the scl pin (scl allowed to float high) during any receive, transmit, or restar t/stop condition. when the scl pin is allowed to float high, the baud rate generator (brg) is suspend ed from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of i2cbrg and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device. 14.12.5 multi-master communication, bus collision, and bus arbitration multi-master operation support is achieved by bus arbitration. when the mast er outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high while another mast er asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the mi2cif pulse and reset the master portion of the i 2 c port to its idle state. if a transmit was in progress when the bus collision occurred, the transmission is halted, the tbf flag is cleared, the sda and scl lines are de-asserted and a value can now be written to i2ctrn. when the user services the i 2 c master event interrupt service routine, if the i 2 c bus is free (i.e., the p bit is set), the user can resume communication by asserting a start condition. if a start, restart, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the i2ccon register are cleared to ? 0 ?. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the mi2cif bit will be set. a write to the i2ctrn will start the transmission of data at the first data bit regardless of where the transmitter left off when bus collision occurred. in a multi-master environment, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the i2cstat register, or the bus is idle and the s and p bits are cleared. 14.13 i 2 c module operation during cpu sleep and idle modes 14.13.1 i 2 c operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shut down and stay at logic ? 0 ?. if sleep occurs in the middle of a transmission and the state machine is partially into a transmission as the clocks stop, then the transmi ssion is aborted. similarly, if sleep occurs in the middle of a reception, then the reception is aborted. 14.13.2 i 2 c operation during cpu idle mode for the i 2 c, the i2csidl bit selects if the module will stop on idle or continue on idle. if i2csidl = 0 , the module will continue operation on assertion of the idle mode. if i2csidl = 1 , the module will stop on idle. i2cbrg = f cy f cy f scl 1,111,111 ? 1 ? () ? 2010 microchip technology inc. ds70139g-page 103 dspic30f2011/2012/3012/3013 table 14-2: i 2 c register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state i2crcv 0200 ? ? ? ? ? ? ? ? receive register 0000 0000 0000 0000 i2ctrn 0202 ? ? ? ? ? ? ? ? transmit register 0000 0000 1111 1111 i2cbrg 0204 ? ? ? ? ? ? ? baud rate generator 0000 0000 0000 0000 i2ccon 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 0001 0000 0000 0000 i2cstat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 0000 0000 0000 i2cadd 020a ? ? ? ? ? ? address register 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual ? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 104 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 105 dspic30f2011/2012/3012/3013 15.0 universal asynchronous receiver transmitter (uart) module this section describes th e universal asynchronous receiver/transmitter communications module. the dspic30f2011/2012/3012 processors have one uart module (uart1). the dspic30f3013 processor has two uart modules (uart1 and uart2). 15.1 uart module overview the key features of the uart module are: ? full-duplex, 8 or 9-bit data communication ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? fully integrated baud rate generator with 16-bit prescaler ? baud rates range from 38 bps to 1.875 mbps at a 30 mhz instruction rate ? 4-word deep transmit data buffer ? 4-word deep receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt only on address detect (9th bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? alternate receive and transmit pins for uart1 figure 15-1: uart transmitter block diagram note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). write write utx8 uxtxreg low byte load tsr transmit control ? control tsr ? control buffer ? generate flags ? generate interrupt control and status bits uxtxif data ? 0 ? (start) ? 1 ? (stop) parity parity generator transmit shift register (uxtsr) 16 divider control signals 16x baud clock from baud rate generator internal data bus utxbrk uxtx note: x = 1 or 2. dspic30f2011/2012/3012/3013 ds70139g-page 106 ? 2010 microchip technology inc. figure 15-2: uart receiver block diagram read urx8 uxrxreg low byte load rsr uxmode receive buffer control ? generate flags ? generate interrupt uxrxif uxrx start bit detect receive shift register 16 divider control signals uxsta ? shift data characters read read write write to buffer 8-9 (uxrsr) perr ferr parity check stop bit detect shift clock generation wake logic 16 internal data bus 1 0 lpback from uxtx 16x baud clock from baud rate generator ? 2010 microchip technology inc. ds70139g-page 107 dspic30f2011/2012/3012/3013 15.2 enabling and setting up uart 15.2.1 enabling the uart the uart module is enabled by setting the uarten bit in the uxmode register (where x = 1 or 2). once enabled, the uxtx and uxrx pins are configured as an output and an input respectively, overriding the tris and lat register bit settings for the corresponding i/o port pins. the uxtx pin is at logic ? 1 ? when no transmission is taking place. 15.2.2 disabling the uart the uart module is disabled by clearing the uarten bit in the uxmode register. this is the default state after any reset. if the uart is disabled, all i/o pins operate as port pins under the control of the lat and tris bits of the corresponding port pins. disabling the uart module resets the buffers to empty states. any data characters in the buffers are lost and the baud rate counter is reset. all error and status flags associated with the uart module are reset when the module is disabled. the urxda, oerr, ferr, perr, utxen, utxbrk and utxbf bits are cleared, whereas ridle and trmt are set. other control bits, including adden, urxisel<1:0>, utxisel, as well as the uxmode and uxbrg registers, are not affected. clearing the uarten bit while the uart is active will abort all pending transmissions and receptions and reset the module as defined above. re-enabling the uart will restart the uart in the same configuration. 15.2.3 alternate i/o the alternate i/o function is enabled by setting the altio bit (uxmode<10>). if altio = 1 , the uxatx and uxarx pins (alternat e transmit and alternate receive pins, respectively) are used by the uart module instead of the uxtx and uxrx pins. if altio = 0 , the uxtx and uxrx pins are used by the uart module. 15.2.4 setting up data, parity and stop bit selections control bits pdsel<1:0> in the uxmode register are used to select the data length and parity used in the transmission. the data length may either be 8 bits with even, odd or no parity, or 9 bits with no parity. the stsel bit determines whether one or two stop bits will be used during data transmission. the default (power-on) setting of the uart is 8 bits, no parity and 1 stop bit (typically represented as 8, n, 1). 15.3 transmitting data 15.3.1 transmitting in 8-bit data mode the following steps must be performed to transmit 8-bit data: 1. set up the uart: first, the data length, pa rity and number of stop bits must be selected. then, the transmit and receive interrupt enable and priority bits are setup in the uxmode and uxsta registers. also, the appropriate baud rate value must be written to the uxbrg register. 2. enable the uart by setting the uarten bit (uxmode<15>). 3. set the utxen bit (uxsta<10>), thereby enabling a transmission. 4. write the byte to be transmitted to the lower byte of uxtxreg. the value will be transferred to the transmit shift register (uxtsr) immediately and the serial bit stream will start shifting out during the next rising edge of the baud clock. alternatively, the data byte may be written while utxen = 0 , following which, the user may set utxen. this will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. 5. a transmit interrupt will be generated, depending on the value of the interrupt control bit utxisel (uxsta<15>). 15.3.2 transmitting in 9-bit data mode the sequence of steps involved in the transmission of 9-bit data is similar to 8-bit transmission, except that a 16-bit data word (of which the upper 7 bits are always clear) must be written to the uxtxreg register. 15.3.3 transmit buffer (u x txb) the transmit buffer is 9 bits wide and 4 characters deep. including the transmit shift register (uxtsr), the user effectively has a 5-deep fifo (f irst-in, first- out) buffer. the utxbf bit (uxsta<9>) indicates whether the transmit buffer is full. if a user attempts to write to a full buffer, the new data will not be accepted into the fifo and no data shift will occur within the buffer. this enables recovery from a buffer overrun condition. the fifo is reset during any device reset, but is not affected when the device enters or wakes up from a power saving mode. dspic30f2011/2012/3012/3013 ds70139g-page 108 ? 2010 microchip technology inc. 15.3.4 transmit interrupt the transmit interrupt flag (u1txif or u2txif) is located in the corresponding interrupt flag register. the transmitter generates an edge to set the uxtxif bit. the condition for generating the interrupt depends on the utxisel control bit: a) if utxisel = 0 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift regist er (uxtsr). this means that the transmit buffer has at least one empty word. b) if utxisel = 1 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift register (uxtsr) and the transmit buffer is empty. switching between the two interrupt modes during operation is possible and sometimes offers more flexibility. 15.3.5 transmit break setting the utxbrk bit (uxsta<11>) will cause the uxtx line to be driven to logic ? 0 ?. the utxbrk bit overrides all transmission activity. therefore, the user should generally wait for the transmitter to be idle before setting utxbrk. to send a break character, the utxbrk bit must be set by software and must rema in set for a minimum of 13 baud clock cycles. the utxbrk bit is then cleared by software to generate stop bits. the user must wait for a duration of at least on e or two baud clock cycles in order to ensure a valid stop bit(s) before reloading the uxtxb, or starting other transmitter activity. transmission of a break character does not generate a transmit interrupt. 15.4 receiving data 15.4.1 receiving in 8-bit or 9-bit data mode the following steps must be performed while receiving 8-bit or 9-bit data: 1. set up the uart (see section 15.3.1 ?transmitting in 8-bit data mode? ). 2. enable the uart (see section 15.3.1 ?transmitting in 8-bit data mode? ). 3. a receive interrupt will be generated when one or more data words have been received, depend- ing on the receive interrupt settings specified by the urxisel bits (uxsta<7:6>). 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in soft- ware. 5. read the received data from uxrxreg. the act of reading uxrxreg will move the next word to the top of the receive fifo, and the perr and ferr values will be updated. 15.4.2 receive buffer (u x rxb) the receive buffer is 4 words deep. including the receive shift register (uxrsr), the user effectively has a 5-word deep fifo buffer. urxda (uxsta<0>) = 1 indicates that the receive buffer has data available. urxda = 0 implies that the buffer is empty. if a user attempts to read an empty buffer, the old values in the buffer will be read and no data shift will occur within the fifo. the fifo is reset during any device reset. it is not affected when the device enters or wakes up from a power saving mode. 15.4.3 receive interrupt the receive interrupt flag (u1rxif or u2rxif) can be read from the corresponding interrupt flag register. the interrupt flag is set by an edge generated by the receiver. the condition for setting the receive interrupt flag depends on the settings specified by the urxisel<1:0> (uxsta<7:6>) control bits. a) if urxisel<1:0> = 00 or 01 , an interrupt is generated every time a data word is transferred from the receive shift register (uxrsr) to the receive buffer. there may be one or more characters in the receive buffer. b) if urxisel<1:0> = 10 , an interrupt is generated when a word is transferred from the receive shift register (uxrsr) to the receive buffer, which as a result of the transfer, contains 3 characters. c) if urxisel<1:0> = 11 , an interrupt is set when a word is transferred from the receive shift register (uxrsr) to the receive buffer, which as a result of the transfer, contains 4 characters (i.e., becomes full). switching between the interrupt modes during operation is possible, though generally not advisable during normal operation. 15.5 reception error handling 15.5.1 receive buffer overrun error (oerr bit) the oerr bit (uxsta<1>) is set if all of the following conditions occur: a) the receive buffer is full. b) the receive shift register is full, but unable to transfer the character to the receive buffer. c) the stop bit of the character in the uxrsr is detected, indicating that the uxrsr needs to transfer the character to the buffer. once oerr is set, no further data is shifted in uxrsr (until the oerr bit is cleared in software or a reset occurs). the data held in uxrsr and uxrxreg remains valid. ? 2010 microchip technology inc. ds70139g-page 109 dspic30f2011/2012/3012/3013 15.5.2 framing error (ferr) the ferr bit (uxsta<2>) is set if a ? 0 ? is detected instead of a stop bit. if two stop bits are selected, both stop bits must be ? 1 ?, otherwise ferr will be set. the read-only ferr bit is buffered along with the received data. it is cleared on any reset. 15.5.3 parity error (perr) the perr bit (uxsta<3>) is set if the parity of the received word is incorrect. this error bit is applicable only if a parity mode (odd or even) is selected. the read-only perr bit is buffered along with the received data bytes. it is cleared on any reset. 15.5.4 idle status when the receiver is active (i.e., between the initial detection of the start bit and the completion of the stop bit), the ridle bit (uxsta<4>) is ? 0 ?. between the com- pletion of the stop bit and detection of the next start bit, the ridle bit is ? 1 ?, indicating that the uart is idle. 15.5.5 receive break the receiver will count and expect a certain number of bit times based on the values programmed in the pdsel (uxmode<2:1>) and stsel (uxmode<0>) bits. if the break is longer than 13 bit times, the reception is considered complete after the number of bit times specified by pdsel and stsel. the urxda bit is set, ferr is set, zeros are loaded into the receive fifo, interrupts are generated if appropriate and the ridle bit is set. when the module receives a long break signal and the receiver has detected the start bit, the data bits and the invalid stop bit (which sets the ferr), the receiver must wait for a valid stop bit before looking for the next start bit. it cannot assume that the break condition on the line is the next start bit. break is regarded as a character containing all ? 0 ?s with the ferr bit set. the break character is loaded into the buffer. no further reception can occur until a stop bit is received. note that ridle goes high when the stop bit has not yet been received. 15.6 address detect mode setting the adden bit (uxsta<5>) enables this special mode in which a 9th bit (urx8) value of ? 1 ? identifies the received word as an address, rather than data. this mode is only applicable for 9-bit data communication. the urxisel control bit does not have any impact on interrupt generation in this mode since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. 15.7 loopback mode setting the lpback bit enab les this special mode in which the uxtx pin is internally connected to the uxrx pin. when configured for the loopback mode, the uxrx pin is disconnected from the internal uart receive logic. however, the uxtx pin still functions as in a normal operation. to select this mode: a) configure uart for desired mode of operation. b) set lpback = 1 to enable loopback mode. c) enable transmission as defined in section 15.3 ?transmitting data? . 15.8 baud rate generator the uart has a 16-bit baud rate generator to allow maximum flexibility in baud rate generation. the baud rate generator register (uxbrg) is readable and writable. the baud rate is computed as follows: brg = 16-bit value held in uxbrg register (0 through 65535) f cy = instruction clock rate (1/t cy ) the baud rate is given by equation 15-1 . equation 15-1: baud rate therefore, the maximum baud rate possible is: f cy /16 (if brg = 0 ), and the minimum baud rate possible is: f cy / (16* 65536). with a full 16-bit baud rate generator at 30 mips operation, the minimum baud rate achievable is 28.5 bps. 15.9 auto-baud support to allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (ic1 for uart1 and ic2 for uart2). to enable this mode, you must program the input capture module to detect the falling and rising edges of the start bit. baud rate = f cy / (16*(brg+1)) dspic30f2011/2012/3012/3013 ds70139g-page 110 ? 2010 microchip technology inc. 15.10 uart operation during cpu sleep and idle modes 15.10.1 uart operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shut down and stay at logic ? 0 ?. if entry into sleep mode occurs while a transmission is in progress, then the transmi ssion is aborted. the uxtx pin is driven to logic ? 1 ?. similarly, if entry into sleep mode occurs while a reception is in progress, then the reception is aborted. the uxsta, uxmode, transmit and receive registers and buffers, and the uxbrg register are not affected by sleep mode. if the wake bit (uxmode<7>) is set before the device enters sleep mode, then a falling edge on the uxrx pin will generate a receive interrupt. the receive interrupt select mode bit (urxisel) has no effect for this function. if the receive interr upt is enabled, then this will wake-up the device from sleep. the uarten bit must be set in order to generate a wake-up interrupt. 15.10.2 uart operation during cpu idle mode for the uart, the usidl bit selects if the module will stop operation when the device enters idle mode or whether the module will continue on idle. if usidl = 0 , the module will continue to operate during idle mode. if usidl = 1 , the module will stop on idle. ? 2010 microchip technology inc. ds70139g-page 111 dspic30f2011/2012/3012/3013 table 15-1: uart1 register map for dspic30f2011/2012/3012/3013 table 15-2: uart2 regist er map for dspic30f3013 (1) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state u1mode 020c uarten ?usidl ? ?altio ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u1sta 020e utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u1txreg 0210 ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u1rxreg 0212 ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u1brg 0214 baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state u2mode 0216 uarten ?usidl ? ? ? ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u2sta 0218 utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u2txreg 021a ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u2rxreg 021c ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u2brg 021e baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note 1: uart2 is not available on dspic30f2011/2012/3012 devices. 2: refer to the ? dspic30f family reference manual? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 112 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 113 dspic30f2011/2012/3012/3013 16.0 12-bit analog-to-digital converter (adc) module the 12-bit analog-to-digital converter allows conversion of an analog input signal to a 12-bit digital number. this module is based on a successive approximation register (sar) architecture and provides a maximum sampling rate of 200 ksps. the adc module has up to 10 analog inputs which are multiplexed into a sample and hold amplifier. the output of the sample and ho ld is the input into the converter which generates the result. the analog reference voltage is software selectable to either the device supply voltage (av dd /av ss ) or the voltage level on the (v ref +/v ref -) pin. the adc has a unique feature of being able to operate while the device is in sleep mode with rc oscillator selection. the adc module has six 16-bit registers: ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) ? a/d control register 3 (adcon3) ? a/d input select register (adchs) ? a/d port configuration register (adpcfg) ? a/d input scan select ion register (adcssl) the adcon1, adcon2 a nd adcon3 registers control the operation of the adc module. the adchs register selects the input channels to be converted. the adpcfg register configures the port pins as analog inputs or as digital i/o. the adcssl register selects inputs for scanning. the block diagram of the 12-bit adc module is shown in figure 16-1 . figure 16-1: 12-bit adc functional block diagram note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). note: the ssrc<2:0>, asam, smpi<3:0>, bufm and alts bits, as well as the adcon3 and adcssl registers, must not be written to while adon = 1 . this would lead to indeterminate results. comparator 12-bit sar conversion logic a vdd /v ref + dac data format 16-word, 12-bit dual port buffer bus interface 0000 0101 0111 1001 0001 0010 0011 0100 0110 1000 an8 an9 an4 an5 an6 an7 an0 an1 an2 an3 ch0 a vss /v ref - sample/sequence control sample input mux control input switches s/h dspic30f2011/2012/3012/3013 ds70139g-page 114 ? 2010 microchip technology inc. 16.1 a/d result buffer the module contains a 16-word dual port read-only buffer, called adcbuf0...adcbuff, to buffer the a/d results. the ram is 12 bits wide but the data obtained is represented in one of fo ur different 16-bit data formats. the contents of the sixteen a/d conversion result buffer registers, adcbuf0 through adcbuff, cannot be written by user software. 16.2 conversion operation after the adc module has been configured, the sample acquisition is started by se tting the samp bit. various sources, such as a programmable bit, timer time-outs and external events, will terminate acquisition and start a conversion. when the a/d conversion is complete, the result is loaded into adcbuf0...adcbuff, and the done bit and the a/d interrupt flag, adif, are set after the number of samples specified by the smpi bit. the adc module can be configured for different inter- rupt rates as described in section 16.3 ?selecting the conversion sequence? . the following steps should be followed for doing an a/d conversion: 1. configure the adc module: ? configure analog pins, voltage reference and digital i/o ? select a/d input channels ? select a/d conversion clock ? select a/d conversion trigger ? turn on adc module 2. configure a/d interrupt (if required): ? clear adif bit ? select a/d interrupt priority 3. start sampling 4. wait the required acquisition time 5. trigger acquisition end, start conversion 6. wait for a/d conversion to complete, by either: ? waiting for the a/d interrupt, or ? waiting for the done bit to get set 7. read a/d result buffer; clear adif if required 16.3 selecting the conversion sequence several groups of control bits select the sequence in which the a/d connects inputs to the sample/hold channel, converts a channel, writes the buffer memory and generates interrupts. the sequence is controlled by the sampling clocks. the smpi bits select the number of acquisition/conversion se quences that would be per- formed before an interrupt occurs. this can vary from 1 sample per interrupt to 16 samples per interrupt. the bufm bit will split the 16-word results buffer into two 8-word groups. writing to the 8-word buffers will be alternated on each interrupt event. use of the bufm bit will depend on how much time is available for the moving of the buffers after the interrupt. if the processor can quickly unload a full buffer within the time it takes to acquire and convert one channel, the bufm bit can be ? 0 ? and up to 16 conversions (corresponding to the 16 input channels) may be done per interrupt. the processor will have one acquisition and conversion time to move the sixteen conversions. if the processor cannot unload the buffer within the acquisition and conversion time, the bufm bit should be ? 1 ?. for example, if smpi<3:0> (adcon2<5:2>) = 0111 , then eight conversions will be loaded into 1/2 of the buffer, following which an interrupt occurs. the next eight conversions will be loaded into the other 1/2 of the buffer. the processor will have the entire time between interrupts to move the eight conversions. the alts bit can be used to alternate the inputs selected during the sampling sequence. the input multiplexer has two sets of sample inputs: mux a and mux b. if the alts bit is ? 0 ?, only the mux a inputs are selected for sampling. if the alts bit is ? 1 ? and smpi<3:0> = 0000 on the first sample/convert sequence, the mux a inputs are selected and on the next acquire/convert sequen ce, the mux b inputs are selected. the cscna bit (adcon2<10>) will allow the multiplexer input to be alternately scanned across a selected number of analog inputs for the mux a group. the inputs are selected by the adcssl register. if a particular bit in the adcssl register is ? 1 ?, the corresponding input is selected. the inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. if the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. ? 2010 microchip technology inc. ds70139g-page 115 dspic30f2011/2012/3012/3013 16.4 programming the start of conversion trigger the conversion trigger will terminate acquisition and start the requested conversions. the ssrc<2:0> bits select the source of the conversion trigger. the ssrc bits provide for up to four alternate sources of conversion trigger. when ssrc<2:0> = 000 , the conversion trigger is under software control. clearing the samp bit will cause the conversion trigger. when ssrc<2:0> = 111 (auto-start mode), the conversion trigger is under a/d clock control. the samc bits select the number of a/d clocks between the start of acquisition and the start of conversion. this provides the fastest conversion rates on multiple channels. samc must always be at least one clock cycle. other trigger sources can come from timer modules or external interrupts. 16.5 aborting a conversion clearing the adon bit during a conversion will abort the current conversion and stop the sampling sequencing until the next sampling trigger. the adcbuf will not be updated with the partially completed a/d conversion sample. that is, the adcbuf will continue to contain the value of the last completed conversion (or the last value written to the adcbuf register). if the clearing of the adon bit coincides with an auto-start, the clearing has a higher priority and a new conversion will not start. after the a/d conversion is aborted, a 2 t ad wait is required before the next sampling may be started by setting the samp bit. 16.6 selecting the adc conversion clock the adc conversion requires 14 t ad . the source of the adc conversion clock is software selected, using a 6-bit counter. there are 64 possible options for t ad . equation 16-1: adc conversion clock the internal rc oscillator is selected by setting the adrc bit. for correct adc conversions, the adc conversion clock (t ad ) must be selected to ensure a minimum t ad time of 334 nsec (for v dd = 5v). refer to section 20.0 ?electrical characteristics? for minimum t ad under other operating conditions. example 16-1 shows a sample calculation for the adcs<5:0> bits, assuming a device operating speed of 30 mips. example 16-1: adc conversion clock and sampling rate calculation t ad = t cy * (0.5*(adcs<5:0> + 1)) minimum t ad = 334 nsec adcs<5:0> = 2 ? 1 t ad t cy t cy = 33 .33 nsec (30 mips) = 2 ? ? 1 334 nsec 33.33 nsec = 19.04 therefore, set adcs<5:0> = 19 actual t ad = (adcs<5:0> + 1) t cy 2 = (19 + 1) 33.33 nsec 2 = 334 nsec if ssrc<2:0> = ?111? and samc<4:0> = ?00001? since, sampling time = acquisition time + conversion time = 1 t ad + 14 t ad = 15 x 334 nsec therefore, sampling rate = = ~200 khz 1 (15 x 334 nsec) dspic30f2011/2012/3012/3013 ds70139g-page 116 ? 2010 microchip technology inc. 16.7 adc speeds the dspic30f 12-bit adc specifications permit a maximum of 200 ksps sampling rate. ta b l e 1 6 - 1 summarizes the conversion speeds for the dspic30f 12-bit adc and the required operating conditions. figure 16-2 depicts the recommended circuit for the conversion rates above 200 ksps. the dspic30f2011 is shown as an example. figure 16-2: adc voltage reference schematic table 16-1: 12-bit adc extended conversion rates dspic30f 12-bit adc conversion rates speed t ad minimum sampling time min r s max v dd temperature channel configuration up to 200 ksps (1) 334 ns 1 t ad 2.5 k 4.5v to 5.5v -40c to +85c up to 100 ksps 668 ns 1 t ad 2.5 k 3.0v to 5.5v -40c to +125c note 1: external v ref - and v ref + pins must be used for correct operation. see figure 16-2 for recommended circuit. v ref -v ref + adc anx s/h ch x v ref -v ref + adc anx s/h ch x anx or v ref - or av ss or av dd v dd v dd v dd c8 1 f v dd c7 0.1 f v dd c6 0.01 f av dd c5 1 f av dd c4 0.1 f av dd c3 0.01 f see note 1: note 1: ensure adequate bypass capacitors are provided on each v dd pin. v ref - 27 26 av dd v ss 23 22 8 9 v dd 11 12 13 14 1 2 3 4 v ss 6 7 21 20 19 18 v dd v ss 15 dspic30f2011 v dd r1 10 v dd r2 10 c2 0.1 f c1 0.01 f ? 2010 microchip technology inc. ds70139g-page 117 dspic30f2011/2012/3012/3013 the configuration procedures in the next section pro- vide the required setup va lues for the conversion speeds above 100 ksps. 16.7.1 200 ksps configuration guideline the following configuration items are required to achieve a 200 ksps conversion rate. ? comply with conditions provided in ta b l e 1 6 - 1 . ? connect external v ref + and v ref - pins following the recommended circuit shown in figure 16-2. ? set ssrc<2.0> = 111 in the adcon1 register to enable the auto convert option. ? enable automatic sampli ng by setting the asam control bit in the adcon1 register. ? write the smpi<3.0> control bits in the adcon2 register for the desired number of conversions between interrupts. ? configure the adc clock period to be: by writing to the adcs<5:0> control bits in the adcon3 register. ? configure the sampling time to be 1 t ad by writing: samc<4:0> = 00001 . the following figure shows the timing diagram of the adc running at 200 ksps. the t ad selection in conjunction with the guidelines described above allows a conversion speed of 200 ksps. see example 16-1 for code example. 16.8 a/d acquisition requirements the analog input model of the 12-bit adc is shown in figure 16-3 . the total sampling time for the a/d is a function of the internal amplifier settling time and the holding capacitor charge time. for the adc to meet its sp ecified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the voltage level on the analog input pin. the source impedance (r s ), the interconnect impedance (r ic ) and the internal sampling switch (r ss ) impedance combine to directly affect the time required to charge the capacitor c hold . the combined impedance of the analog s ources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. to minimize the effects of pin leakage currents on the accuracy of the adc, the maximum recommended source impedance, r s , is 2.5 k . after the analog input channel is selected (changed), this sampling function must be completed prior to starting the conversion. the internal holding capacitor will be in a disch arged state prior to each sample operation. figure 16-3: 12-bit a/d converter analog input model 1 (14 + 1) x 200,000 = 334 ns c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic 250 sampling switch r ss c hold = dac capacitance v ss v dd = 18 pf 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample/hold capacitance (from dac) various junctions note: c pin value depends on device package and is not tested. effect of c pin negligible if rs 2.5 k . r ss 3 k dspic30f2011/2012/3012/3013 ds70139g-page 118 ? 2010 microchip technology inc. 16.9 module power-down modes the module has two internal power modes. when the adon bit is ? 1 ?, the module is in active mode; it is fully powered and functional. when adon is ? 0 ?, the module is in off mode. the digital and analog portions of the circuit are disabled for maximum current savings. in order to return to the active mode from off mode, the user must wait for the adc circuitry to stabilize. 16.10 a/d operation during cpu sleep and idle modes 16.10.1 a/d operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shut down and stay at logic ? 0 ?. if sleep occurs in the middle of a conversion, the conversion is aborted. t he converter will not continue with a partially completed conversion on exit from sleep mode. register contents are not affected by the device entering or leaving sleep mode. the adc module can operate during sleep mode if the a/d clock source is set to rc (adrc = 1 ). when the rc clock source is selected, the adc module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed which eliminates all digital switching noise from the conversion. when the conversion is complete, the conv bit will be cleared and the result loaded into the adcbuf register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the adc module will then be turned off, although the adon bit will remain set. 16.10.2 a/d operation during cpu idle mode the adsidl bit selects if the module will stop on idle or continue on idle. if adsidl = 0 , the module will continue operation on asse rtion of idle mode. if adsidl = 1 , the module will stop on idle. 16.11 effects of a reset a device reset forces all re gisters to their reset state. this forces the adc module to be turned off, and any conversion and sampling sequence is aborted. the values that are in the adcbuf registers are not modified. the a/d result register will contain unknown data after a power-on reset. 16.12 output formats the a/d result is 12 bits wide. the data buffer ram is also 12 bits wide. the 12-bit data can be read in one of four different formats. the form<1:0> bits select the format. each of the output formats translates to a 16-bit result on the data bus. figure 16-4: a/d output data formats ram contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 read to bus: signed fractional d11 d10d09d08d07d06d05d04d03d02d01d000000 fractional d11d10d09d08d07d06d05d04d03d02d01d000000 signed integer d11 d11 d11 d11 d11 d10d09d08d07d06d05d04d03d02d01d00 integer 0000d11d10d09d08d07d06d05d04d03d02d01d00 ? 2010 microchip technology inc. ds70139g-page 119 dspic30f2011/2012/3012/3013 16.13 configuring analog port pins the use of the adpcfg and tr is registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independe nt of the state of the ch0sa<3:0>/ch0sb<3:0> bits and the tris bits. when reading the port register, all pins configured as analog input channels will read as cleared. pins configured as digital inputs will not convert an analog input. analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. 16.14 connection considerations the analog inputs have diodes to v dd and v ss as esd protection. this requires that the analog input be between v dd and v ss . if the input voltage exceeds this range by greater than 0.3v (either direction), one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded. an external rc filter is sometimes added for anti-aliasing of the input signal. the r component should be selected to ensure that the sampling time requirements are satisfied. any external components connected (via high-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. dspic30f2011/2012/3012/3013 ds70139g-page 120 ? 2010 microchip technology inc. table 16-2: a/d converter regist er map for dspic30f2011/3012 sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state adcbuf0 0280 ? ? ? ? adc data buffer 0 0000 uuuu uuuu uuuu adcbuf1 0282 ? ? ? ? adc data buffer 1 0000 uuuu uuuu uuuu adcbuf2 0284 ? ? ? ? adc data buffer 2 0000 uuuu uuuu uuuu adcbuf3 0286 ? ? ? ? adc data buffer 3 0000 uuuu uuuu uuuu adcbuf4 0288 ? ? ? ? adc data buffer 4 0000 uuuu uuuu uuuu adcbuf5 028a ? ? ? ? adc data buffer 5 0000 uuuu uuuu uuuu adcbuf6 028c ? ? ? ? adc data buffer 6 0000 uuuu uuuu uuuu adcbuf7 028e ? ? ? ? adc data buffer 7 0000 uuuu uuuu uuuu adcbuf8 0290 ? ? ? ? adc data buffer 8 0000 uuuu uuuu uuuu adcbuf9 0292 ? ? ? ? adc data buffer 9 0000 uuuu uuuu uuuu adcbufa 0294 ? ? ? ? adc data buffer 10 0000 uuuu uuuu uuuu adcbufb 0296 ? ? ? ? adc data buffer 11 0000 uuuu uuuu uuuu adcbufc 0298 ? ? ? ? adc data buffer 12 0000 uuuu uuuu uuuu adcbufd 029a ? ? ? ? adc data buffer 13 0000 uuuu uuuu uuuu adcbufe 029c ? ? ? ? adc data buffer 14 0000 uuuu uuuu uuuu adcbuff 029e ? ? ? ? adc data buffer 15 0000 uuuu uuuu uuuu adcon1 02a0 adon ?adsidl ? ? ? form<1:0> ssrc<2:0> ? ? asam samp done 0000 0000 0000 0000 adcon2 02a2 vcfg<2:0> ? ? cscna ? ?bufs ? smpi<3:0> bufm alts 0000 0000 0000 0000 adcon3 02a4 ? ? ? samc<4:0> adrc ? adcs<5:0> 0000 0000 0000 0000 adchs 02a6 ? ? ? ch0nb ch0sb<3:0> ? ? ? ch0na ch0sa<3:0> 0000 0000 0000 0000 adpcfg 02a8 ? ? ? ? ? ? ? ? pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 adcssl 02aa ? ? ? ? ? ? ? ? cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual? (ds70046) for descriptions of register bit fields. ? 2010 microchip technology inc. ds70139g-page 121 dspic30f2011/2012/3012/3013 table 16-3: a/d converter register map for dspic30f2012/3013 sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state adcbuf0 0280 ? ? ? ? adc data buffer 0 0000 uuuu uuuu uuuu adcbuf1 0282 ? ? ? ? adc data buffer 1 0000 uuuu uuuu uuuu adcbuf2 0284 ? ? ? ? adc data buffer 2 0000 uuuu uuuu uuuu adcbuf3 0286 ? ? ? ? adc data buffer 3 0000 uuuu uuuu uuuu adcbuf4 0288 ? ? ? ? adc data buffer 4 0000 uuuu uuuu uuuu adcbuf5 028a ? ? ? ? adc data buffer 5 0000 uuuu uuuu uuuu adcbuf6 028c ? ? ? ? adc data buffer 6 0000 uuuu uuuu uuuu adcbuf7 028e ? ? ? ? adc data buffer 7 0000 uuuu uuuu uuuu adcbuf8 0290 ? ? ? ? adc data buffer 8 0000 uuuu uuuu uuuu adcbuf9 0292 ? ? ? ? adc data buffer 9 0000 uuuu uuuu uuuu adcbufa 0294 ? ? ? ? adc data buffer 10 0000 uuuu uuuu uuuu adcbufb 0296 ? ? ? ? adc data buffer 11 0000 uuuu uuuu uuuu adcbufc 0298 ? ? ? ? adc data buffer 12 0000 uuuu uuuu uuuu adcbufd 029a ? ? ? ? adc data buffer 13 0000 uuuu uuuu uuuu adcbufe 029c ? ? ? ? adc data buffer 14 0000 uuuu uuuu uuuu adcbuff 029e ? ? ? ? adc data buffer 15 0000 uuuu uuuu uuuu adcon1 02a0 adon ?adsidl ? ? ? form<1:0> ssrc<2:0> ? ? asam samp done 0000 0000 0000 0000 adcon2 02a2 vcfg<2:0> ? ? cscna ? ?bufs ? smpi<3:0> bufm alts 0000 0000 0000 0000 adcon3 02a4 ? ? ? samc<4:0> adrc ? adcs<5:0> 0000 0000 0000 0000 adchs 02a6 ? ? ? ch0nb ch0sb<3:0> ? ? ? ch0na ch0sa<3:0> 0000 0000 0000 0000 adpcfg 02a8 ? ? ? ? ? ? pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 adcssl 02aa ? ? ? ? ? ? cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 0000 0000 0000 legend: u = uninitialized bit; ? = unimplemented bit, read as ? 0 ? note: refer to the ? dspic30f family reference manual? (ds70046) for descriptions of register bit fields. dspic30f2011/2012/3012/3013 ds70139g-page 122 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 123 dspic30f2011/2012/3012/3013 17.0 system integration there are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - programmable brown-out reset (bor) ? watchdog timer (wdt) ? low-voltage detect ? power-saving modes (sleep and idle) ? code protection ? unit id locations ? in-circuit serial programming (icsp) dspic30f devices have a watchdog timer which is permanently enabled via the configuration bits or can be software controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt) which provides a delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit a wide variety of applications. in the idle mode, the clock sources are still active but the cpu is shut-off. the rc oscillator option saves system cost wh ile the lp crystal option saves power. 17.1 oscillator system overview the dspic30f oscillator system has the following modules and features: ? various external and internal oscillator options as clock sources ? an on-chip pll to boost internal operating frequency ? a clock switching mech anism between various clock sources ? programmable clock post scaler for system power savings ? a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures ? clock control register (osccon) ? configuration bits for main oscillator selection configuration bits determine the clock source upon power-on reset (por) and brown-out reset (bor). thereafter, the clock source can be changed between permissible clock sources. the osccon register controls the clock switching and reflects system clock related status bits. table 17-1 provides a summary of the dspic30f oscillator operating modes. a simplified diagram of the oscillator system is shown in figure 17-1 . note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? 16-bit mcu and dsc programmer?s reference manual? (ds70157). dspic30f2011/2012/3012/3013 ds70139g-page 124 ? 2010 microchip technology inc. table 17-1: oscillator operating modes oscillator mode description xtl xt xt w/pll 4x xt w/pll 8x xt w/pll 16x lp hs 200 khz-4 mhz crystal on osc1:osc2. 4 mhz-10 mhz crystal on osc1:osc2. 4 mhz-10 mhz crystal on osc1:osc2, 4x pll enabled. 4 mhz-10 mhz crystal on osc1:osc2, 8x pll enabled. 4 mhz-7.5 mhz crystal on osc1:osc2, 16x pll enabled (1) . 32 khz crystal on sosco:sosci (2) . 10 mhz-25 mhz crystal. hs/2 w/pll 4x hs/2 w/pll 8x hs/2 w/pll 16x 10 mhz-20 mhz crystal, divide by 2, 4x pll enabled. 10 mhz-20 mhz crystal, divide by 2, 8x pll enabled. 10 mhz-15 mhz crystal, divide by 2, 16x pll enabled (1) . hs/3 w/pll 4x hs/3 w/pll 8x hs/3 w/pll 16x 12 mhz-25 mhz crystal, divide by 3, 4x pll enabled. 12 mhz-25 mhz crystal, divide by 3, 8x pll enabled. 12 mhz-22.5 mhz crystal, divide by 3, 16x pll enabled (1) . ec ecio ec w/pll 4x ec w/pll 8x ec w/pll 16x erc ercio external clock input (0-40 mhz). external clock input (0-40 mhz), osc2 pin is i/o. external clock input (4-10 mhz), osc2 pin is i/o, 4x pll enabled. external clock input (4-10 mhz), osc2 pin is i/o, 8x pll enabled. external clock input (4-7.5 mhz), osc2 pin is i/o, 16x pll enabled (1) . external rc oscillator, osc2 pin is f osc /4 output (3) . external rc oscillator, osc2 pin is i/o (3) . frc frc w/pll 4x frc w/pll 8x frc w/pll 16x 7.37 mhz internal rc oscillator. 7.37 mhz internal rc oscillator, 4x pll enabled. 7.37 mhz internal rc oscillator, 8x pll enabled. 7.37 mhz internal rc oscillator, 16x pll enabled. lprc 512 khz internal rc oscillator. note 1: dspic30f maximum operating fr equency of 120 mhz must be met. 2: lp oscillator can be conveniently shared as system clock, as well as real-time clock for timer1. 3: requires external r and c. frequency operation up to 4 mhz. ? 2010 microchip technology inc. ds70139g-page 125 dspic30f2011/2012/3012/3013 figure 17-1: oscillator system block diagram primary osc1 osc2 sosco sosci oscillator 32 khz lp clock and control block switching oscillator x4, x8, x16 pll primary oscillator stability detector stability detector secondary oscillator programmable clock divider oscillator start-up timer fail-safe clock monitor (fscm) internal fast rc oscillator (frc) internal low power rc oscillator (lprc) pwrsav instruction wake-up request oscillator configuration bits system clock oscillator trap to timer1 lprc secondary osc por done primary osc f pll post<1:0> 2 fcksm<1:0> 2 pll lock cosc<2:0> nosc<2:0> oswen cf internal frc osc dspic30f2011/2012/3012/3013 ds70139g-page 126 ? 2010 microchip technology inc. 17.2 oscillator configurations 17.2.1 initial clock source selection while coming out of power-on reset or brown-out reset, the device selects its clock source based on: a) fos<2:0> configuration bits that select one of four oscillator groups, b) and fpr<4:0> configuratio n bits that select one of 15 oscillator choices within the primary group. the selection is as shown in table 17-2 . 17.2.2 oscillator start-up timer (ost) in order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer is included. it is a simple 10-bit counter that counts 1024 t osc cycles before releasing the oscillator clock to the rest of the system. the time-out period is designated as t ost . the t ost time is involved every time the oscillator has to restart (i.e., on por, bor and wake-up from sleep). the oscillator start-up timer is applied to the lp oscillator, xt, xtl and hs modes (upon wake-up from sleep, por and bor) for the primary oscillator. table 17-2: configuration bit values for clock selection oscillator mode oscillator source fos<2:0> fpr<4:0> osc2 function ecio w/pll 4x pll 1 1 101101 i/o ecio w/pll 8x pll 1 1 101110 i/o ecio w/pll 16x pll 1 1 101111 i/o frc w/pll 4x pll 1 1 100001 i/o frc w/pll 8x pll 1 1 101010 i/o frc w/pll 16x pll 1 1 100011 i/o xt w/pll 4x pll 1 1 100101 osc2 xt w/pll 8x pll 1 1 100110 osc2 xt w/pll 16x pll 1 1 100111 osc2 hs2 w/pll 4x pll 1 1 110001 osc2 hs2 w/pll 8x pll 1 1 110010 osc2 hs2 w/ pll 16x pll 1 1 110011 osc2 hs3 w/pll 4x pll 1 1 110101 osc2 hs3 w/pll 8x pll 1 1 110110 osc2 hs3 w/pll 16x pll 1 1 110111 osc2 ecio external 0 1 101100 i/o xt external 0 1 100100 osc2 hs external 0 1 100010 osc2 ec external 0 1 101011 clko erc external 0 1 101001 clko ercio external 0 1 101000 i/o xtl external 0 1 100000 osc2 lp secondary 0 0 0xxxxx (note 1, 2) frc internal frc 0 0 1xxxxx (note 1, 2) lprc internal lprc 0 1 0xxxxx (note 1, 2) note 1: the osc2 pin is either usable as a general purpose i/o pin or is completely unusable, depending on the primary oscillator mode selection (fpr<4:0>). 2: osc1 pin cannot be used as an i/o pin even if the seco ndary oscillator or an in ternal clock source is selected at all times. ? 2010 microchip technology inc. ds70139g-page 127 dspic30f2011/2012/3012/3013 17.2.3 lp oscillator control enabling the lp oscillator is controlled with two elements: ? the current oscillator group bits cosc<2:0>. ? the lposcen bit (osccon register). the lp oscillator is on (even during sleep mode) if lposcen = 1. the lp oscillator is the device clock if: ?cosc<2:0> = 000 (lp selected as main osc.) and ? lposcen = 1 keeping the lp oscillator on at all times allows for a fast switch to the 32 khz system clock for lower power oper- ation. returning to the faster main oscillator will still require a start-up time 17.2.4 phase locked loop (pll) the pll multiplies the cloc k which is generated by the primary oscillator or fast rc oscillator. the pll is selectable to have either gains of x4, x8, and x16. input and output frequency ranges are summarized in table 17-3 . table 17-3: pll frequency range the pll features a lock out put which is asserted when the pll enters a phase locked state. should the loop fall out of lock (e.g., due to noise), the lock signal will be rescinded. the state of this signal is reflected in the read-only lock bit in the osccon register. 17.2.5 fast rc oscillator (frc) the frc oscillator is a fast (7.37 mhz 2% nominal) internal rc oscillator. this oscillator is intended to provide reasonable device operating speeds without the use of an external crystal, ceramic resonator, or rc network. the frc oscillator can be used with the pll to obtain higher clock frequencies. the dspic30f operates from the frc oscillator when- ever the current oscillator selection control bits in the osccon register (osccon<14:12>) are set to ? 001 ?. the four bit field specified by tun<3:0> (osctun <3:0>) allows the user to tune the internal fast rc oscillator (nominal 7.37 mhz). the user can tune the frc oscillator within a range of +10.5% (840 khz) and -12% (960 khz) in steps of 1.50% around the factory calibrated setting, as shown in table 17-4 . if osccon<14:12> are set to ? 111 ? and fpr<4:0> are set to ? 00001 ?, ? 01010 ? or ? 00011 ?, a pll multiplier of 4, 8 or 16 (respectively) is applied. table 17-4: frc tuning 17.2.6 low-power rc oscillator (lprc) the lprc oscillator is a component of the watchdog timer (wdt) and oscillates at a nominal frequency of 512 khz. the lprc oscillator is the clock source for the power-up timer (pwrt) circuit, wdt and clock monitor circuits. it may also be used to provide a low-frequency clock source option for applications where power consumption is critical and timing accuracy is not required. the lprc oscillator is always enabled at a power-on reset because it is the cl ock source for the pwrt. after the pwrt expires, the lprc oscillator will remain on if one of the following is true: ? the fail-safe clock monitor is enabled ? the wdt is enabled ? the lprc oscillator is selected as the system clock via the cosc<2:0> control bits in the osccon register if one of the above conditio ns is not true, the lprc will shut-off after the pwrt expires. f in pll multiplier f out 4 mhz-10 mhz x4 16 mhz-40 mhz 4 mhz-10 mhz x8 32 mhz-80 mhz 4 mhz-7.5 mhz x16 64 mhz-120 mhz note: osctun functionality has been provided to help customers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tuning step size is an approximation and is neither characterized nor tested. note: when a 16x pll is used, the frc fre- quency must not be tuned to a frequency greater than 7.5 mhz. tun<3:0> bits frc frequency 0111 + 10.5% 0110 + 9.0% 0101 + 7.5% 0100 + 6.0% 0011 + 4.5% 0010 + 3.0% 0001 + 1.5% 0000 center frequency (oscillator is running at calibrated frequency) 1111 - 1.5% 1110 - 3.0% 1101 - 4.5% 1100 - 6.0% 1011 - 7.5% 1010 - 9.0% 1001 - 10.5% 1000 - 12.0% note 1: osc2 pin function is determined by the primary oscillator mode selection (fpr<4:0>). 2: osc1 pin cannot be used as an i/o pin even if the secondary oscillator or an internal clock source is selected at all times. dspic30f2011/2012/3012/3013 ds70139g-page 128 ? 2010 microchip technology inc. 17.2.7 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by appropriately programming the fcksm configuration bits (clock switch and monitor selection bits) in the fosc device configuration register. if t he fscm function is enabled, the lprc internal oscillator will run at all times (except during sleep mode) and will not be subject to control by the swdten bit. in the event of an oscillator failure, the fscm will gen- erate a clock failure trap event and will switch the sys- tem clock over to the frc oscillator. the user will then have the option to either attempt to restart the oscillator or execute a controlled shut down. the user may decide to treat the trap as a warm reset by simply loading the reset address into the oscillato r fail trap vector. in this event, the cf (clock fail) bit (osccon<3>) is also set whenever a clock failure is recognized. in the event of a clock failure, the wdt is unaffected and continues to run on the lprc clock. if the oscillator has a very slow start-up time coming out of por, bor or sleep, it is possible that the pwrt timer will expire before the oscillator has started. in such cases, the fscm will be activated and the fscm will initiate a clock failure trap, and the cosc<2:0> bits are loaded with frc oscillator selection. this will effectively shut-off the original oscillator that was trying to start. the user may detect this situation and restart the oscillator in the clock fail trap isr. upon a clock failure detection, the fscm module will initiate a clock switch to the frc oscillator as follows: 1. the cosc bits (osccon<14:12>) are loaded with the frc oscillator selection value. 2. cf bit is set (osccon<3>). 3. oswen control bit (osccon<0>) is cleared. for the purpose of clock s witching, the clock sources are sectioned into four groups: ? primary (with or without pll) ? secondary ? internal frc ? internal lprc the user can switch between these functional groups but cannot switch between op tions within a group. if the primary group is selected, then the choice within the group is always determined by the fpr<4:0> configuration bits. the osccon register holds the control and status bits related to clock switching. ? cosc<2:0>: read-only bits always reflect the current oscillator group in effect. ? nosc<2:0>: control bits which are written to indicate the new oscillator group of choice. - on por and bor, cosc<2:0> and nosc<2:0> are both loaded with the configuration bit values fos<2:0>. ? lock: the lock bit indicates a pll lock. ? cf: read-only bit indicating if a clock fail detect has occurred. ? oswen: control bit changes from a ? 0 ? to a ? 1 ? when a clock transition sequence is initiated. clearing the oswen control bit will abort a clock transition in progress (used for hang-up situations). if configuration bits fcksm<1:0> = 1x , then the clock switching and fail-safe clock monitoring functions are disabled. this is the default configuration bit setting. if clock switching is disabl ed, then the fos<2:0> and fpr<4:0> bits directly control the oscillator selection and the cosc<2:0> bits do not control the clock selec- tion. however, these bits will reflect the clock source selection. 17.2.8 protection against accidental writes to osccon a write to the osccon register is intentionally made difficult because it controls clock switching and clock scaling. to write to the osccon low byte, the following code sequence must be execut ed without any other instructions in between: byte write 0x46 to osccon low byte write 0x57 to osccon low byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. to write to the osccon high byte, the following instructions must be ex ecuted without any other instructions in between: byte write 0x78 to osccon high byte write 0x9a to osccon high byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. note: the application should not attempt to switch to a clock of frequency lower than 100 khz when the fail-safe clock monitor is enabled. if such clock switching is performed, the device may generate an oscillator fail trap and switch to the fast rc oscillator. ? 2010 microchip technology inc. ds70139g-page 129 dspic30f2011/2012/3012/3013 17.3 reset the dspic30f2011/2012/3012/3013 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) reset caused by trap lockup (trapr) h) reset caused by illegal opcode or by using an uninitialized w register as an address pointer (iopuwr) different registers are affected in different ways by various reset conditions. most registers are not affected by a wdt wake-up since this is viewed as the resumption of normal operation. status bits from the rcon register are set or cleared differently in different reset situations, as indicated in table 17-5 . these bits are used in software to determine the nature of the reset. a block diagram of the on-chip reset circuit is shown in figure 17-2 . a mclr noise filter is provided in the mclr reset path. the filter detects and ignores small pulses. internally generated resets do not drive mclr pin low. 17.3.1 por: power-on reset a power-on event will generate an internal por pulse when a v dd rise is detected. the reset pulse will occur at the por circuit threshold voltage (v por ) which is nominally 1.85v. the device supply voltage characteristics must meet specified starting voltage and rise rate requirements. the por pulse will reset a por timer and place the device in the reset state. the por also selects the device clock source identified by the oscillator configuration fuses. the por circuit inserts a small delay, t por , which is nominally 10 s and ensures that the device bias circuits are stable. furthermore, a user selected power-up time-out (t pwrt ) is applied. the t pwrt parameter is based on device configuration bits and can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. the total delay is at device power-up, t por + t pwrt . when these delays have expired, sysrst will be negated on the next leading edge of the q1 clock and the pc will jump to the reset vector. the timing for the sysrst signal is shown in figure 17-3 through figure 17-5. figure 17-2: reset system block diagram s r q mclr v dd v dd rise detect por sysrst sleep or idle brown-out reset boren reset instruction wdt module digital glitch filter bor trap conflict illegal opcode/ uninitialized w register dspic30f2011/2012/3012/3013 ds70139g-page 130 ? 2010 microchip technology inc. figure 17-3: time-out sequence on power-up (mclr tied to v dd ) figure 17-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 17-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost ? 2010 microchip technology inc. ds70139g-page 131 dspic30f2011/2012/3012/3013 17.3.1.1 por with long cr ystal start-up time (with fscm enabled) the oscillator start-up circuitry is not linked to the por circuitry. some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after the por timer and the pwrt have expired: ? the oscillator circuit has not begun to oscillate. ? the oscillator start-up timer has not expired (if a crystal oscillator is used). ? the pll has not achieved a lock (if pll is used). if the fscm is enabled and one of the above conditions is true, then a clock failure trap will occur. the device will automatically switch to the frc oscillator and the user can switch to the desired crystal oscillator in the trap isr. 17.3.1.2 operating without fscm and pwrt if the fscm is disabled and the power-up timer (pwrt) is also disabled, th en the device will exit rap- idly from reset on power-up. if the clock source is frc, lprc, erc or ec, it will be active immediately. if the fscm is disabled and the system clock has not started, the device will be in a frozen state at the reset vector until the system clo ck starts. from the user?s perspective, the device will appear to be in reset until a system clock is available. 17.3.2 bor: programmable brown-out reset the bor (brown-out reset) module is based on an internal voltage reference circuit. the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (i.e., missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). the bor module allows selection of one of the following voltage trip points (see table 20-11 ): ? 2.6v-2.71v ? 4.1v-4.4v ? 4.58v-4.73v a bor will generate a reset pulse which will reset the device. the bor will select the clock source based on the device configuration bit values (fos<2:0> and fpr<4:0>). furthermore, if an oscillator mode is selected, the bor will activate the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, then the clock will be held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the por time-out (t por ) and the pwrt time-out (t pwrt ) will be applied before the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm = 100 s is applied. the total delay in this case is (t por + t fscm ). the bor status bit (rcon<1>) will be set to indicate that a bor has occurred. t he bor circuit, if enabled, will continue to operate while in sleep or idle modes and will reset the device should v dd fall below the bor threshold voltage. figure 17-6: external power-on reset circuit (for slow v dd power-up) note: the bor voltage trip points indicated here are nominal values provided for design guidance only. refer to the electrical specifications in t he specific device data sheet for bor voltage limit specifications. note: dedicated supervisory devices, such as the mcp1xx and mcp8xx, may also be used as an external power-on reset circuit. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r should be suitably chosen so as to make sure that the voltage drop across r does not violate the device?s elec trical specifications. 3: r1 should be suitably chosen so as to limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd dspic30f mclr dspic30f2011/2012/3012/3013 ds70139g-page 132 ? 2010 microchip technology inc. table 17-5 shows the reset co nditions for the rcon register. since the control bi ts within the rcon register are r/w, the information in the table means that all the bits are negated prior to the action specified in the condition column. table 17-5: initialization condit ion for rcon register: case 1 table 17-6 shows a second example of the bit conditions for the rcon register. in this case, it is not assumed the user has set/clea red specific bits prior to action specified in the condition column. table 17-6: initialization condit ion for rcon register: case 2 condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 000000011 brown-out reset 0x000000 000000001 mclr reset during normal operation 0x000000 001000000 software reset during normal operation 0x000000 000100000 mclr reset during sleep 0x000000 001000100 mclr reset during idle 0x000000 001001000 wdt time-out reset 0x000000 000010000 wdt wake-up pc + 2 000010100 interrupt wake-up from sleep pc + 2 (1) 000000100 clock failure trap 0x000004 000000000 trap reset 0x000000 100000000 illegal operation trap 0x000000 010000000 note 1: when the wake-up is due to an enabled interrupt, the pc is loaded with the corresponding interrupt vector. condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 000000011 brown-out reset 0x000000 uuuuuuu01 mclr reset during normal operation 0x000000 uu10000uu software reset during normal operation 0x000000 uu01000uu mclr reset during sleep 0x000000 uu1u001uu mclr reset during idle 0x000000 uu1u010uu wdt time-out reset 0x000000 uu00100uu wdt wake-up pc + 2 uuuu1u1uu interrupt wake-up from sleep pc + 2 (1) uuuuuu1uu clock failure trap 0x000004 uuuuuuuuu trap reset 0x000000 1uuuuuuuu illegal operation reset 0x000000 u1uuuuuuu legend: u = unchanged note 1: when the wake-up is due to an enabled interrupt, the pc is loaded with the corresponding interrupt vector. ? 2010 microchip technology inc. ds70139g-page 133 dspic30f2011/2012/3012/3013 17.4 watchdog timer (wdt) 17.4.1 watchdog timer operation the primary function of the watchdog timer (wdt) is to reset the processor in the event of a software malfunction. the wdt is a free-running timer which runs off an on-chip rc oscillator, requiring no external component. therefor e, the wdt timer will continue to operate even if the main processor clock (e.g., the crystal oscillator) fails. 17.4.2 enabling and disabling the wdt the watchdog timer can be ?enabled? or ?disabled? only through a configuration bit (fwdten) in the configuration register, fwdt. setting fwdten = 1 enables the watchdog timer. the enabling is done when programming the device. by default, after chip erase, fwdten bit = 1 . any device programmer capable of programming dspic30f devices allows programming of this and other configuration bits. if enabled, the wdt will incr ement until it overflows or ?times out?. a wdt time-out will force a device reset (except during sleep). to prevent a wdt time-out, the user must clear the watchdog timer using a clrwdt instruction. if a wdt times out during sleep, the device will wake-up. the wdto bit in the rcon register will be cleared to indicate a wake-up resulting from a wdt time-out. setting fwdten = 0 allows user software to enable/disable the watchdog timer via the swdten (rcon<5>) control bit. 17.5 low-voltage detect the low-voltage detect (lvd) module is used to detect when the v dd of the device drops below a threshold value, v lvd , which is determined by the lvdl<3:0> bits (rcon<11:8>) and is thus user pro- grammable. the internal voltage reference circuitry requires a nominal amount of time to stabilize, and the bgst bit (rcon<13>) indicates when the voltage reference has stabilized. in some devices, the lvd threshold voltage may be applied externally on the lvdin pin. the lvd module is enabled by setting the lvden bit (rcon<12>). 17.6 power-saving modes there are two power-saving states that can be entered through the execution of a special instruction, pwrsav ; these are sleep and idle. the format of the pwrsav instruction is as follows: pwrsav dspic30f2011/2012/3012/3013 ds70139g-page 134 ? 2010 microchip technology inc. any interrupt that is individually enabled (using the corresponding ie bit) and meets the prevailing priority level will be able to wake-up the processor. the processor will process the interrupt and branch to the isr. the sleep status bit in the rcon register is set upon wake-up. all resets will wake-up the processor from sleep mode. any reset, other than por, will set the sleep status bit. in a por, the sleep bit is cleared. if the watchdog timer is enabled, then the processor will wake-up from sleep mode upon wdt time-out. the sleep and wdto status bits are both set. 17.6.2 idle mode in idle mode, the clock to the cpu is shut down while peripherals keep running. unlike sleep mode, the clock source remains active. several peripherals have a control bit in each module that allows them to operate during idle. lprc fail-safe clock remains active if clock failure detect is enabled. the processor wakes up from id le if at least one of the following conditions has occurred: ? any interrupt that is individually enabled (ie bit is ? 1 ?) and meets the required priority level ? any reset (por, bor, mclr ) ? wdt time-out upon wake-up from idle mode, the clock is re-applied to the cpu and instruction execution begins immediately, starting with the instruction following the pwrsav instruction. any interrupt that is individually enabled (using ie bit) and meets the prevailing priority level will be able to wake-up the processor. the processor will process the interrupt and branch to the isr. the idle status bit in the rcon register is set upon wake-up. any reset other than por will set the idle status bit. on a por, the idle bit is cleared. if watchdog timer is enabled, then the processor will wake-up from idle mode upon wdt time-out. the idle and wdto status bits are both set. unlike wake-up from sleep, there are no time delays involved in wake-up from idle. 17.7 device configuration registers the configuration bits in each device configuration register specify some of the device modes and are programmed by a device programmer, or by using the in-circuit serial progra mming? (icsp?) feature of the device. each device configuration register is a 24-bit register, but only the lower 16 bits of each register are used to hold co nfiguration data. there are five device configuration registers available to the user: 1. fosc (0xf80000): oscillator configuration register 2. fwdt (0xf80002): watchdog timer configuration register 3. fborpor (0xf80004): bor and por configuration register 4. fgs (0xf8000a): general code segment configuration register 5. ficd (0xf8000c): debug configuration register the placement of the configuration bits is automatically handled when you select the device in your device programmer. the desired state of the configuration bits may be specified in the source code (dependent on the language tool used), or through the programming interface. after the device has been programmed, the application software may read the configuration bit values through the table read instructions. for additional information, please refer to the programming specifications of the device. note: in spite of various delays applied (t por , t lock and t pwrt ), the crystal oscillator (and pll) may not be active at the end of the time-out (e.g., for low-frequency crystals). in such cases, if fscm is enabled, then the device will detect this as a clock failure and process the clock failure trap, the frc oscillator will be enabled and the user will have to re-enable the crystal oscillator. if fscm is not enabled, then the device will simply suspend execution of code until the clock is stable and will remain in sleep until the oscillator clock has started. note: if the code protection configuration fuse bits (fgs ? 2010 microchip technology inc. ds70139g-page 135 dspic30f2011/2012/3012/3013 17.8 peripheral module disable (pmd) registers the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled via the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the cont rol and status registers associated with the peripheral will also be disabled so writes to those registers will have no effect and read values will be invalid. a peripheral module will only be enabled if both the associated bit in the pmd register is cleared and the peripheral is supported by the specific dspic dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. 17.9 in-circuit debugger when mplab ? icd 2 is selected as a debugger, the in-circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. when the device has this feature enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. one of four pairs of debug i/o pins may be selected by the user using configurat ion options in mplab ide. these pin pairs are named emud/emuc, emud1/emuc1, emud2/emuc2 and emud3/emuc3. in each case, the selected emud pin is the emulation/debug data line, and the emuc pin is the emulation/debug clock line. these pins will interface to the mplab icd 2 module available from microchip. the selected pair of debug i/o pins is used by mplab icd 2 to send commands and receive responses, as well as to send and receive data. to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , pgc, pgd and the selected emudx/emucx pin pair. this gives rise to two possibilities: 1. if emud/emuc is selected as the debug i/o pin pair, then only a 5-pin interface is required, as the emud and emuc pin functions are multi- plexed with the pgd and pgc pin functions in all dspic30f devices. 2. if emud1/emuc1, emud2/emuc2 or emud3/emuc3 is selected as the debug i/o pin pair, then a 7-pin interface is required, as the emudx/emucx pin functions (x = 1, 2 or 3) are not multiplexed with the pgd and pgc pin functions. note 1: if a pmd bit is set, the corresponding module is disabled after a delay of 1 instruction cycle. similarly, if a pmd bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control reg- isters are already configured to enable module operation). 2: in dspic30f2011, dspic30f3012 and dspic30f2012 devices, the u2md bit is readable and writable and will be read as ? 1 ? when set. dspic30f2011/2012/3012/3013 ds70139g-page 136 ? 2010 microchip technology inc. table 17-7: system inte gration register map table 17-8: device configuration register map sfr name address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state rcon 0740 trapr iopuwr bgst lvden lvdl<3:0> extr swr swdten wdto sleep idle bor por (note 1) osccon 0742 ?cosc<2:0> ? nosc<2:0> post<1:0> lock ?cf ? lposcen oswen (note 2) osctun 0744 ? ? ? ? ? ? ? ? ? ? ? ? tun3 tun2 tun1 tun0 (note 2) pmd1 0770 ? ? t3md t2md t1md ? ? ? i2cmd u2md (3) u1md ? spi1md ? ? adcmd 0000 0000 0000 0000 pmd2 0772 ? ? ? ? ? ?ic2mdic1md ? ? ? ? ? ?oc2mdoc1md 0000 0000 0000 0000 legend: ? = unimplemented bit, read as ? 0 ? note 1: reset state depends on type of reset. 2: reset state depends on configuration bits. 3: only available on ds pic30f3013 devices. name address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fosc f80000 fcksm<1:0> ? ? ? fos<2:0> ? ? ? fpr<4:0> fwdt f80002 fwdten ? ? ? ? ? ? ? ? ? fwpsa<1:0> fwpsb<3:0> fborpor f80004 mclren ? ? ? ? pwmpin (1) hpol (1) lpol (1) boren ?borv<1:0> ? ?fpwrt<1:0> fbs f80006 ? ? reserved (2) ? ? ? reserved (2) ? ? ? ? reserved (2) fss f80008 ? ? reserved (2) ? ? reserved (2) ? ? ? ? reserved (2) fgs f8000a ? ? ? ? ? ? ? ? ? ? ? ? ? reserved (3) gcp gwrp ficd f8000c bkbug coe ? ? ? ? ? ? ? ? ? ? ? ?ics<1:0> legend: ? = unimplemented bit, read as ? 0 ? note 1: these bits are reserved (read as ? 1 ? and must be programmed as ? 1 ?). 2: reserved bits read as ? 1 ? and must be programmed as ? 1 ?. 3: the fgs<2> bit is a read-only copy of the gcp bit (fgs<1>). ? 2010 microchip technology inc. ds70139g-page 137 dspic30f2011/2012/3012/3013 18.0 instruction set summary the dspic30f instruction set adds many enhancements to the previous pic ? mcu instruction sets, while maintaining an easy migration from pic mcu instruction sets. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word in struction is a 24-bit word divided into an 8-bit opcode which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 18-1 shows the general symbols used in describing the instructions. the dspic30f instruct ion set summary in ta b l e 1 8 - 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriente d w register instructions (including barrel shift instructions) have three operands: ? the first source operand which is typically a register ?wb? without any address modifier ? the second source operand which is typically a register ?ws? with or without an address modifier ? the destination of the result which is typically a register ?wd? with or wit hout an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value ?f? ? the destination, which c ould either be the file register ?f? or the w0 regi ster, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand which is a register ?wb? without any address modifier ? the second source operand which is a literal value ? the destination of the result (only if not the same as the first source operand) which is typically a register ?wd? with or without an address modifier the mac class of dsp instructio ns may use some of the following operands: ? the accumulator (a or b) to be used (required operand) ? the w registers to be used as the two operands ? the x and y address space prefetch operations ? the x and y address space prefetch destinations ? the accumulator write-back destination the other dsp instructions do not involve any multiplication, and may include: ? the accumulator to be used (required) ? the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier ? the amount of shift specif ied by a w register ?wn? or a literal value the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summ arizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register descriptions and general device functionality, refer to the ? dspic30f family reference manual? (ds70046). for more information on the device instruction set and programming, refer to the ? dspic30f programmer?s reference manual? (ds70030). dspic30f2011/2012/3012/3013 ds70139g-page 138 ? 2010 microchip technology inc. all instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (unconditional/com puted branch), indirect call/goto , all table reads and writes, and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either tw o or three cycles if the skip is performed, depending on wh ether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: for more details on the instruction set, refer to the ?mcu and dsc programmer?s reference manual? (ds70157). table 18-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation ? 2010 microchip technology inc. ds70139g-page 139 dspic30f2011/2012/3012/3013 wb base w register {w0..w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working register pair (direct addressing) wm*wm multiplicand and multiplier working register pair for square instructions {w4*w4,w5*w5,w6*w6,w7*w7} wm*wn multiplicand and multiplier working register pair for dsp instructions {w4*w5,w4*w6,w4*w7,w5*w6,w5*w7,w6*w7} wn one of 16 working registers {w0..w15} wnd one of 16 destination working registers {w0..w15} wns one of 16 source working registers {w0..w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws --], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions {[w8]+=6, [w8]+=4, [w8]+=2, [w8], [w8]-=6, [w8]-=4, [w8]-=2, [w9]+=6, [w9]+=4, [w9]+=2, [w9], [w9]-=6, [w9]-=4, [w9]-=2, [w9+w12],none} wxd x data space prefetch destinati on register for dsp instructions {w4..w7} wy y data space prefetch address register for dsp instructions {[w10]+=6, [w10]+=4, [w10]+=2, [w10], [w10]-=6, [w10]-=4, [w10]-=2, [w11]+=6, [w11]+=4, [w11]+=2 , [w11], [w11]-=6, [w11]-=4, [w11]-=2, [w11+w12], none} wyd y data space prefetch destination register for dsp instructions {w4..w7} table 18-1: symbols used in opcode descriptions (continued) field description dspic30f2011/2012/3012/3013 ds70139g-page 140 ? 2010 microchip technology inc. table 18-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected 1add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws ? 2010 microchip technology inc. ds70139g-page 141 dspic30f2011/2012/3012/3013 9btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws dspic30f2011/2012/3012/3013 ds70139g-page 142 ? 2010 microchip technology inc. 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit14,expr do code to pc+expr, lit14+1 times 2 2 none do wn,expr do code to pc+expr, (wn)+1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 none 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd , awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 n,z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n,z mov.d wns,wd move double from w(ns):w(ns+1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd+1):w(nd) 1 2 none 47 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none table 18-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected ? 2010 microchip technology inc. ds70139g-page 143 dspic30f2011/2012/3012/3013 48 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 49 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd -(multiply wm by wn) to accumulator 1 1 none 50 msc msc wm*wm,acc,wx,wxd,wy,wyd , awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 51 mul mul.ss wb,ws,wnd {wnd+1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 11 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 11 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 11 none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 11 none mul f w3:w2 = f * wreg 1 1 none 52 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 53 nop nop no operation 1 1 none nopr no operation 1 1 none 54 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd+1) 12 none pop.s pop shadow registers 1 1 all 55 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 56 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 57 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 58 repeat repeat #lit14 repeat next instruction lit14+1 times 1 1 none repeat wn repeat next instruction (wn)+1 times 1 1 none 59 reset reset software device reset 1 1 none 60 retfie retfie return from interrupt 1 3 (2) none 61 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 62 return return return from subroutine 1 3 (2) none 63 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 64 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 65 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z table 18-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected dspic30f2011/2012/3012/3013 ds70139g-page 144 ? 2010 microchip technology inc. 66 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 67 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 68 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 69 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 70 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 71 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 72 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f - wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f - wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn - lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb - ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb - lit5 1 1 c,dc,n,ov,z 73 subb subb f f = f - wreg - (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f - wreg - (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn - lit10 - (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb - ws - (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb - lit5 - (c ) 1 1 c,dc,n,ov,z 74 subr subr f f = wreg - f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg - f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws - wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 - wb 1 1 c,dc,n,ov,z 75 subbr subbr f f = wreg - f - (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg -f - (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws - wb - (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 - wb - (c ) 1 1 c,dc,n,ov,z 76 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 77 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 78 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 79 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 80 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 81 ulnk ulnk unlink frame pointer 1 1 none 82 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 83 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 18-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycle s status flags affected ? 2010 microchip technology inc. ds70139g-page 145 dspic30f2011/2012/3012/3013 19.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 19.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. dspic30f2011/2012/3012/3013 ds70139g-page 146 ? 2010 microchip technology inc. 19.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 19.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 19.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 19.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 19.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility ? 2010 microchip technology inc. ds70139g-page 147 dspic30f2011/2012/3012/3013 19.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 19.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 19.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 19.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. dspic30f2011/2012/3012/3013 ds70139g-page 148 ? 2010 microchip technology inc. 19.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 19.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 19.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. ? 2010 microchip technology inc. ds70139g-page 149 dspic30f2011/2012/3012/3013 20.0 electrical characteristics this section provides an overview of dspic30f electrical char acteristics. additional informa tion will be provided in future revisions of this document as it becomes available. for detailed information about the dspic30f architecture and core, refer to the ?dspic30f family reference manual? (ds70046). absolute maximum ratings for the dspic30f family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional opera tion of the device at these or any other conditions above the parameters indicated in the operation list ings of this specification is not implied. absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) (note 1) ..................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +5.5v voltage on mclr with respect to v ss ........................................................................................................ 0v to +13.25v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (note 2) ................................................................................................................250 ma input clamp current, i ik (v i < 0 or v i > v dd ) .......................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ................................................................................................... 20 ma maximum output current sunk by any i/o pin............. ........................................................................ .....................25 ma maximum output current sourced by any i/o pin .......... ........................................................................ ..................25 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (note 2) ....................................................................................................200 ma note 1: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . 2: maximum allowable current is a function of device maximum powe r dissipation. see table 20-2 for p dmax . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or an y other conditi ons above those indicated in the operation listings of th is specification is not im plied. exposure to maximum rating conditions for extended periods may affect device reliability. note: all peripheral electrical characteristics are specif ied. for exact peripherals available on specific devices, please refer to the dspic30f2011/2012/3012/3013 sensor family table on page 4 of this data sheet. dspic30f2011/2012/3012/3013 ds70139g-page 150 ? 2010 microchip technology inc. 20.1 dc characteristics table 20-1: operating mips vs. voltage v dd range temp range max mips dspic30fxxx-30i dspic30fxxx-20e 4.5-5.5v -40c to 85c 30 ? 4.5-5.5v -40c to 125c ? 20 3.0-3.6v -40c to 85c 20 ? 3.0-3.6v -40c to 125c ? 15 2.5-3.0v -40c to 85c 10 ? table 20-2: thermal operating conditions rating symbol min typ max unit dspic30f201x-30i dspic30f301x-30i operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c dspic30f201x-20e dspic30f301x-20e operating junction temperature range t j -40 ? +150 c operating ambient temperature range t a -40 ? +125 c power dissipation: internal chip power dissipation: p d p int + p i / o w i/o pin power dissipation: maximum allowed power dissipation p dmax (t j - t a ) / ja w p int v dd i dd i oh ? () = p i / o v dd v oh ? {} i oh () v ol i ol () + = table 20-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistan ce, 18-pin pdip (p) ja 44 ? c/w 1 package thermal resistan ce, 18-pin soic (so) ja 57 ? c/w 1 package thermal resistan ce, 28-pin spdip (sp) ja 42 ? c/w 1 package thermal resist ance, 28-pin (soic) ja 49 ? c/w 1 package thermal resi stance, 44-pin qfn ja 28 ? c/w 1 note 1: junction to ambient thermal resistance, theta-ja ( ja ) numbers are achieved by package simulations. ? 2010 microchip technology inc. ds70139g-page 151 dspic30f2011/2012/3012/3013 table 20-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage (2) dc10 v dd supply voltage 2.5 ? 5.5 v industrial temperature dc11 v dd supply voltage 3.0 ? 5.5 v extended temperature dc12 v dr ram data retention voltage (3) 1.75 ? ? v dc16 v por v dd start voltage (to ensure internal power-on reset signal) ??v ss v dc17 s vdd v dd rise rate (to ensure internal power-on reset signal) 0.05 ? ? v/ms 0-5v in 0.1 sec 0-3v in 60 ms note 1: ?typ? column data is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: this is the limit to which v dd can be lowered without losing ram data. dspic30f2011/2012/3012/3013 ds70139g-page 152 ? 2010 microchip technology inc. table 20-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) dc31a 1.6 3.0 ma 25c 3.3v 0.128 mips lprc (512 khz) dc31b 1.6 3.0 ma 85c dc31c 1.6 3.0 ma 125c dc31e 3.6 6.0 ma 25c 5v dc31f 3.3 6.0 ma 85c dc31g 3.2 6.0 ma 125c dc30a 3.0 5.0 ma 25c 3.3v (1.8 mips) frc (7.37 mhz) dc30b 3.0 5.0 ma 85c dc30c 3.1 5.0 ma 125c dc30e 6.0 9.0 ma 25c 5v dc30f 5.8 9.0 ma 85c dc30g 5.7 9.0 ma 125c dc23a 9.0 15.0 ma 25c 3.3v 4 mips dc23b 10.0 15.0 ma 85c dc23c 10.0 15.0 ma 125c dc23e 16.0 24.0 ma 25c 5v dc23f 16.0 24.0 ma 85c dc23g 16.0 24.0 ma 125c dc24a 22.0 33.0 ma 25c 3.3v 10 mips dc24b 22.0 33.0 ma 85c dc24c 22.0 33.0 ma 125c dc24e 37.0 56.0 ma 25c 5v dc24f 37.0 56.0 ma 85c dc24g 37.0 56.0 ma 125c dc27a 41.0 60.0 ma 25c 3.3v 20 mips dc27b 40.0 60.0 ma 85c dc27d 68.0 90.0 ma 25c 5v dc27e 67.0 90.0 ma 85c dc27f 66.0 90.0 ma 125c dc29a 96.0 140.0 ma 25c 5v 30 mips dc29b 94.0 140.0 ma 85c note 1: data in ?typical? column is at 5v, 25c unless other wise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operati ng voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern a nd temperature also have an impact on the current consumpti on. the test conditions for all i dd measurements are as follows: osc1 driven with external square wave from rail to rail. all i/o pins are configured as inputs and pulled to v dd . mclr = v dd , wdt, fscm, lvd and bor are disabled. cpu, sram, program memory and data memory are operational. no peripheral modules are operating. ? 2010 microchip technology inc. ds70139g-page 153 dspic30f2011/2012/3012/3013 table 20-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) dc51a 1.3 2.5 ma 25c 3.3v 0.128 mips lprc (512 khz) dc51b 1.3 2.5 ma 85c dc51c 1.2 2.5 ma 125c dc51e 3.2 5.0 ma 25c 5v dc51f 2.9 5.0 ma 85c dc51g 2.8 5.0 ma 125c dc50a 3.0 5.0 ma 25c 3.3v (1.8 mips) frc (7.37 mhz) dc50b 3.0 5.0 ma 85c dc50c 3.0 5.0 ma 125c dc50e 6.0 9.0 ma 25c 5v dc50f 5.8 9.0 ma 85c dc50g 5.7 9.0 ma 125c dc43a 5.2 8.0 ma 25c 3.3v 4 mips dc43b 5.3 8.0 ma 85c dc43c 5.4 8.0 ma 125c dc43e 9.7 15.0 ma 25c 5v dc43f 9.6 15.0 ma 85c dc43g 9.5 15.0 ma 125c dc44a 11.0 17.0 ma 25c 3.3v 10 mips dc44b 11.0 17.0 ma 85c dc44c 11.0 17.0 ma 125c dc44e 19.0 29.0 ma 25c 5v dc44f 19.0 29.0 ma 85c dc44g 20.0 30.0 ma 125c dc47a 20.0 35.0 ma 25c 3.3v 20 mips dc47b 21.0 35.0 ma 85c dc47d 35.0 50.0 ma 25c 5v dc47e 36.0 50.0 ma 85c dc47f 36.0 50.0 ma 125c dc49a 51.0 70.0 ma 25c 5v 30 mips dc49b 51.0 70.0 ma 85c note 1: data in ?typical? column is at 5v, 25c unless other wise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on and all modules turned off. dspic30f2011/2012/3012/3013 ds70139g-page 154 ? 2010 microchip technology inc. table 20-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions power-down current (i pd ) (2) dc60a 0.3 ? a 25c 3.3v base power-down current (3) dc60b 1.3 30.0 a 85c dc60c 16.0 60.0 a125c dc60e 0.5 ? a 25c 5v dc60f 3.7 45.0 a 85c dc60g 25.0 90.0 a125c dc61a 6.0 9.0 a 25c 3.3v watchdog timer current: i wdt (3) dc61b 6.0 9.0 a 85c dc61c 6.0 9.0 a125c dc61e 13.0 20.0 a 25c 5v dc61f 12.0 20.0 a 85c dc61g 12.0 20.0 a125c dc62a 4.0 10.0 a 25c 3.3v timer1 w/32 khz crystal: i ti 32 (3) dc62b 5.0 10.0 a 85c dc62c 4.0 10.0 a125c dc62e 4.0 15.0 a 25c 5v dc62f 6.0 15.0 a 85c dc62g 5.0 15.0 a125c dc63a 33.0 53.0 a 25c 3.3v bor on: i bor (3) dc63b 35.0 53.0 a 85c dc63c 19.0 53.0 a125c dc63e 38.0 62.0 a 25c 5v dc63f 41.0 62.0 a 85c dc63g 41.0 62.0 a125c dc66a 21.0 40.0 a 25c 3.3v low-voltage detect: i lvd (3) dc66b 26.0 40.0 a 85c dc66c 27.0 40.0 a125c dc66e 25.0 44.0 a 25c 5v dc66f 27.0 44.0 a 85c dc66g 29.0 44.0 a125c note 1: data in the typical column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripheral s and clocks shut down . all i/os are configured as inputs and pulled high. lvd, bor, wdt, etc. are all switched off. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. ? 2010 microchip technology inc. ds70139g-page 155 dspic30f2011/2012/3012/3013 table 20-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage (2) di10 i/o pins: with schmitt trigger buffer v ss ?0.2v dd v di15 mclr v ss ?0.2v dd v di16 osc1 (in xt, hs and lp modes) v ss ?0.2v dd v di17 osc1 (in rc mode) (3) v ss ?0.3v dd v di18 sda, scl v ss ?0.3v dd v sm bus disabled di19 sda, scl v ss ? 0.8 v sm bus enabled v ih input high voltage (2) di20 i/o pins: with schmitt trigger buffer 0.8 v dd ?v dd v di25 mclr 0.8 v dd ?v dd v di26 osc1 (in xt, hs and lp modes) 0.7 v dd ?v dd v di27 osc1 (in rc mode) (3) 0.9 v dd ?v dd v di28 sda, scl 0.7 v dd ?v dd v sm bus disabled di29 sda, scl 2.1 ? v dd v sm bus enabled i cnpu cn xx pull-up current (2) di30 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (2)(4)(5) di50 i/o ports ? 0.01 1 av ss v pin v dd , pin at high impedance di51 analog input pins ? 0.50 ? av ss v pin v dd , pin at high impedance di55 mclr ?0.055 av ss v pin v dd di56 osc1 ? 0.05 5 av ss v pin v dd , xt, hs and lp osc mode note 1: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: in rc oscillator configuration, the osc1/clkl pin is a schmitt trigger input. it is not recommended that the dspic30f device be driven with an external clock while in rc mode. 4: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating co nditions. higher leakage current may be measured at different input voltages. 5: negative current is defined as current sourced by the pin. dspic30f2011/2012/3012/3013 ds70139g-page 156 ? 2010 microchip technology inc. table 20-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v ol output low voltage (2) do10 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 5v ? ? 0.15 v i ol = 2.0 ma, v dd = 3v do16 osc2/clko ? ? 0.6 v i ol = 1.6 ma, v dd = 5v (rc or ec osc mode) ? ? 0.72 v i ol = 2.0 ma, v dd = 3v v oh output high voltage (2) do20 i/o ports v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 5v v dd ? 0.2 ? ? v i oh = -2.0 ma, v dd = 3v do26 osc2/clko v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 5v (rc or ec osc mode) v dd ? 0.1 ? ? v i oh = -2.0 ma, v dd = 3v capacitive loading specs on output pins (2) do50 c osc 2 osc2/sosc2 pin ? ? 15 pf in xtl, xt, hs and lp modes when external clock is used to drive osc1. do56 c io all i/o pins and osc2 ? ? 50 pf rc or ec osc mode do58 c b scl, sda ? ? 400 pf in i 2 c mode note 1: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. ? 2010 microchip technology inc. ds70139g-page 157 dspic30f2011/2012/3012/3013 figure 20-1: low-voltage detect characteristics table 20-10: electrical characteristics: lvdl dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions lv10 v plvd lvdl voltage on v dd transition high-to-low lvdl = 0000 (2) ???v lvdl = 0001 (2) ???v lvdl = 0010 (2) ???v lvdl = 0011 (2) ???v lvdl = 0100 2.50 ? 2.65 v lvdl = 0101 2.70 ? 2.86 v lvdl = 0110 2.80 ? 2.97 v lvdl = 0111 3.00 ? 3.18 v lvdl = 1000 3.30 ? 3.50 v lvdl = 1001 3.50 ? 3.71 v lvdl = 1010 3.60 ? 3.82 v lvdl = 1011 3.80 ? 4.03 v lvdl = 1100 4.00 ? 4.24 v lvdl = 1101 4.20 ? 4.45 v lvdl = 1110 4.50 ? 4.77 v lv15 v lvdin external lvd input pin threshold voltage lvdl = 1111 ???v note 1: these parameters are characterized but not tested in manufacturing. 2: these values not in usable operating range. lv10 lvdif v dd (lvdif set by hardware) dspic30f2011/2012/3012/3013 ds70139g-page 158 ? 2010 microchip technology inc. figure 20-2: brown-out reset characteristics table 20-11: electrical characteristics: bor dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions bo10 v bor bor voltage (2) on v dd transition high to low borv = 11 (3) ? ? ? v not in operating range borv = 10 2.6 ? 2.71 v borv = 01 4.1 ? 4.4 v borv = 00 4.58 ? 4.73 v bo15 v bhys ?5?mv note 1: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: 11 values not in usable operating range. bo10 reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) power-up time-out bo15 ? 2010 microchip technology inc. ds70139g-page 159 dspic30f2011/2012/3012/3013 table 20-12: dc characteristics: program and eeprom dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions data eeprom memory (2) d120 e d byte endurance 100k 1m ? e/w -40 c t a +85c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time 0.8 2 2.6 ms rtsp d123 t retd characteristic retention 40 100 ? year provided no other specifications are violated d124 i dew i dd during programming ? 10 30 ma row erase program flash memory (2) d130 e p cell endurance 10k 100k ? e/w -40 c t a +85c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v eb v dd for bulk erase 4.5 ? 5.5 v d133 v pew v dd for erase/write 3.0 ? 5.5 v d134 t pew erase/write cycle time 0.8 2 2.6 ms rtsp d135 t retd characteristic retention 40 100 ? year provided no other specifications are violated d137 i pew i dd during programming ? 10 30 ma row erase d138 i eb i dd during programming ? 10 30 ma bulk erase note 1: data in ?typ? column is at 5v, 25c unless otherwise stated. 2: these parameters are characterized but not tested in manufacturing. dspic30f2011/2012/3012/3013 ds70139g-page 160 ? 2010 microchip technology inc. 20.2 ac characteristics and timing parameters the information contained in this section defines dspic30f ac characteristics and timing parameters. table 20-13: temperature and voltage specifications ? ac figure 20-3: load conditions for device timing specifications figure 20-4: external clock timing ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended operating voltage v dd range as described in section 20.1 ?dc characteristics? . v dd /2 c l r l pin pin v ss v ss c l legend: r l =464 c l = 50 pf for all pins except osc2 5 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 osc1 clko q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31 ? 2010 microchip technology inc. ds70139g-page 161 dspic30f2011/2012/3012/3013 table 20-14: external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os10 f osc external clkn frequency (2) (external clocks allowed only in ec mode) dc 4 4 4 ? ? ? ? 40 10 10 7.5 mhz mhz mhz mhz ec ec with 4x pll ec with 8x pll ec with 16x pll oscillator frequency (2) dc 0.4 4 4 4 4 10 10 10 10 12 12 12 31 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 7.37 7.37 7.37 7.37 512 4 4 10 10 10 7.5 25 20 20 15 25 25 22.5 33 ? ? ? ? ? mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz khz mhz mhz mhz mhz khz rc xtl xt xt with 4x pll xt with 8x pll xt with 16x pll hs hs/2 with 4x pll hs/2 with 8x pll hs/2 with 16x pll hs/3 with 4x pll hs/3 with 8x pll hs/3 with 16x pll lp frc internal frc internal w/4x pll frc internal w/8x pll frc internal w/16x pll lprc internal os20 t osc t osc = 1/f osc ? ? ? ? see parameter os10 for f osc value os25 t cy instruction cycle time (2)(3) 33 ? dc ns see table 20-17 os30 tosl, to s h external clock (2) in (osc1) high or low time .45 x t osc ??nsec os31 tosr, to s f external clock (2) in (osc1) rise or fall time ? ? 20 ns ec os40 tckr clko rise time (2)(4) ? ? ? ns see parameter do31 os41 tckf clko fall time (2)(4) ? ? ? ns see parameter do32 note 1: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data fo r that particular oscillator type under standard operating conditions with the device executing code. exc eeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/c lki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 4: measurements are taken in ec or erc modes. the cl ko signal is measured on the osc2 pin. clko is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ). dspic30f2011/2012/3012/3013 ds70139g-page 162 ? 2010 microchip technology inc. table 20-15: pll clock timing specifications (v dd = 2.5 to 5.5 v) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range (2) 4 4 4 4 4 4 5 (3) 5 (3) 5 (3) 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? 10 10 7.5 (4) 10 10 7.5 (4) 10 10 7.5 (4) 8.33 (3) 8.33 (3) 7.5 (4) mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz ec with 4x pll ec with 8x pll ec with 16x pll xt with 4x pll xt with 8x pll xt with 16x pll hs/2 with 4x pll hs/2 with 8x pll hs/2 with 16x pll hs/3 with 4x pll hs/3 with 8x pll hs/3 with 16x pll os51 f sys on-chip pll output (2) 16 ? 120 mhz ec, xt, hs/2, hs/3 modes with pll os52 t loc pll start-up time (lock time) ? 20 50 s note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: limited by oscillator frequency range. 4: limited by device operating frequency range. table 20-16: pll jitter ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ (1) max units conditions os61 x4 pll ? 0.251 0.413 % -40c t a +85c v dd = 3.0 to 3.6v ? 0.251 0.413 % -40c t a +125c v dd = 3.0 to 3.6v ? 0.256 0.47 % -40c t a +85c v dd = 4.5 to 5.5v ? 0.256 0.47 % -40c t a +125c v dd = 4.5 to 5.5v x8 pll ? 0.355 0.584 % -40c t a +85c v dd = 3.0 to 3.6v ? 0.355 0.584 % -40c t a +125c v dd = 3.0 to 3.6v ? 0.362 0.664 % -40c t a +85c v dd = 4.5 to 5.5v ? 0.362 0.664 % -40c t a +125c v dd = 4.5 to 5.5v x16 pll ? 0.67 0.92 % -40c t a +85c v dd = 3.0 to 3.6v ? 0.632 0.956 % -40c t a +85c v dd = 4.5 to 5.5v ? 0.632 0.956 % -40c t a +125c v dd = 4.5 to 5.5v note 1: these parameters are characterized but not tested in manufacturing. ? 2010 microchip technology inc. ds70139g-page 163 dspic30f2011/2012/3012/3013 table 20-17: internal clock timing examples clock oscillator mode f osc (mhz) (1) t cy ( sec) (2) mips (3) w/o pll mips (3) w pll x4 mips (3) w pll x8 mips (3) w pll x16 ec 0.200 20.0 0.05 ? ? ? 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 ? 25 0.16 6.25 ? ? ? xt 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 ? note 1: assumption: oscillator postscaler is divide by 1. 2: instruction execution cycle time: t cy = 1/mips. 3: instruction execution frequency: mips = (f osc * pllx)/4 [since there ar e 4 q clocks per instruction cycle]. table 20-18: ac characteristics: internal frc accuracy ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ frc freq. = 7.37 mhz (1) os63 frc ? ? 2.00 % -40c t a +85c v dd = 3.0-5.5v ? ? 5.00 % -40c t a +125c v dd = 3.0-5.5v note 1: frequency calibrated at 7.372 mhz 2%, 25c and 5v. tun bits (osccon<3:0>) can be used to compensate for temperature drift. table 20-19: ac characteristics: internal lprc accuracy ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. characteristic min typ max units conditions lprc @ freq. = 512 khz (1) os65a -50 ? +50 % v dd = 5.0v, 10% os65b -60 ? +60 % v dd = 3.3v, 10% os65c -70 ? +70 % v dd = 2.5v note 1: change of lprc frequency as v dd changes. dspic30f2011/2012/3012/3013 ds70139g-page 164 ? 2010 microchip technology inc. figure 20-5: clko and i/o timing characteristics table 20-20: clko and i/o timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1)(2)(3) min typ (4) max units conditions do31 t io r port output rise time ? 7 20 ns do32 t io f port output fall time ? 7 20 ns di35 t inp intx pin high or low time (output) 20 ? ? ns di40 t rbp cnx high or low time (input) 2 t cy ??ns note 1: these parameters are asynchronous events not related to any internal clock edges 2: measurements are taken in rc mode and ec mode where clko output is 4 x t osc . 3: these parameters are characterized but not tested in manufacturing. 4: data in ?typ? column is at 5v, 25c unless otherwise stated. note: refer to figure 20-3 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 ? 2010 microchip technology inc. ds70139g-page 165 dspic30f2011/2012/3012/3013 figure 20-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing characteristics table 20-21: reset, watchdog timer, osci llator start-up timer, power-up timer and brown-out reset timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy10 tmcl mclr pulse width (low) 2 ? ? s -40c to +85c sy11 t pwrt power-up timer period 2 10 43 4 16 64 8 32 128 ms -40c to +85c, v dd = 5v user programmable sy12 t por power on reset delay 3 10 30 s -40c to +85c sy13 t ioz i/o high impedance from mclr low or watchdog timer reset ?0.81.0 s sy20 t wdt 1 t wdt 2 t wdt 3 watchdog timer time-out period (no prescaler) 1.1 1.2 1.3 2.0 2.0 2.0 6.6 5.0 4.0 ms ms ms v dd = 2.5v v dd = 3.3v, 10% v dd = 5v, 10% sy25 t bor brown-out reset pulse width (3) 100 ? ? sv dd v bor (d034) sy30 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period sy35 t fscm fail-safe clock monitor delay ? 500 900 s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. 3: refer to figure 20-2 and ta b l e 2 0 - 11 for bor. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 20-3 for load conditions. fscm delay sy35 sy30 sy12 dspic30f2011/2012/3012/3013 ds70139g-page 166 ? 2010 microchip technology inc. figure 20-7: band gap start-up time characteristics table 20-22: band gap start-up time requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy40 t bgap band gap start-up time ? 40 65 s defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. rcon<13> bit note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. v bgap enable band gap band gap 0v (see note) stable note: set lvden bit (rcon<12 >) or fborpor<7>set. sy40 ? 2010 microchip technology inc. ds70139g-page 167 dspic30f2011/2012/3012/3013 figure 20-8: type a, b and c timer external clock timing characteristics table 20-23: type a timer (timer1) exte rnal clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta11 t tx l txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta15 t tx p txck input period synchronous, no prescaler t cy + 10 ? ? ns synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n ? ? ? n = prescale value (1, 8, 64, 256) asynchronous 20 ? ? ns os60 ft1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting bit tcs (t1con, bit 1)) dc ? 50 khz ta20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy ?1.5 t cy ? note: timer1 is a type a. note: refer to figure 20-3 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck dspic30f2011/2012/3012/3013 ds70139g-page 168 ? 2010 microchip technology inc. table 20-24: type b timer (timer2 and timer4) external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic mi n typ max units conditions tb10 ttxh txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb11 ttxl txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb15 ttxp txck input period synchronous, no prescaler t cy + 10 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tb20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy ? 1.5 t cy ? note: timer2 and timer4 are type b. table 20-25: type c timer (timer3 and timer5) external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions tc10 ttxh txck high time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, no prescaler t cy + 10 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tc20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy ?1.5 t cy ? note: timer3 and timer5 are type c. ? 2010 microchip technology inc. ds70139g-page 169 dspic30f2011/2012/3012/3013 figure 20-9: input capture (capx) timing characteristics table 20-26: input capture timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic15 tccp icx input period (2 t cy + 40)/n ? ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. ic x ic10 ic11 ic15 note: refer to figure 20-3 for load conditions. dspic30f2011/2012/3012/3013 ds70139g-page 170 ? 2010 microchip technology inc. figure 20-10: output compare module (ocx) timing characteristics table 20-27: output compare module timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc10 tccf ocx output fall time ? ? ? ns see parameter do32 oc11 tccr ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 20-3 for load conditions. or pwm mode) ? 2010 microchip technology inc. ds70139g-page 171 dspic30f2011/2012/3012/3013 figure 20-11: oc/pwm module timing characteristics table 20-28: simple oc/pwm mode timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc15 t fd fault input to pwm i/o change ??50ns oc20 t flt fault input pulse width 50 ? ? ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. ocfa/ocfb ocx oc20 oc15 dspic30f2011/2012/3012/3013 ds70139g-page 172 ? 2010 microchip technology inc. figure 20-12: spi module master mode (cke = 0 ) timing characteristics table 20-29: spi master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy /2 ? ? ns ? sp11 tsch sck x output high time (3) t cy /2 ? ? ns ? sp20 tscf sck x output fall time (4 ? ? ? ns see parameter do32 sp21 tscr sck x output rise time (4) ? ? ? ns see parameter do31 sp30 tdof sdo x data output fall time (4) ? ? ? ns see parameter do32 sp31 tdor sdo x data output rise time (4) ? ? ? ns see parameter do31 sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 20-3 for load conditions. ? 2010 microchip technology inc. ds70139g-page 173 dspic30f2011/2012/3012/3013 figure 20-13: spi module master mode (cke = 1 ) timing characteristics table 20-30: spi module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy /2 ? ? ns ? sp11 tsch sck x output high time (3) t cy /2 ? ? ns ? sp20 tscf sck x output fall time (4) ? ? ? ns see parameter do32 sp21 tscr sck x output rise time (4) ? ? ? ns see parameter do31 sp30 tdof sdo x data output fall time (4) ? ? ? ns see parameter do32 sp31 tdor sdo x data output rise time (4) ? ? ? ns see parameter do31 sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ??30ns ? sp36 tdov2sc, tdov2scl sdo x data output setup to first sck x edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb msb in bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 20-3 for load conditions. sp11 sp10 sp20 sp21 sp21 sp20 sp40 sp41 dspic30f2011/2012/3012/3013 ds70139g-page 174 ? 2010 microchip technology inc. figure 20-14: spi module slave mode (cke = 0 ) timing characteristics table 20-31: spi module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscl sck x input low time 30 ? ? ns ? sp71 tsch sck x input high time 30 ? ? ns ? sp72 tscf sck x input fall time (3) ?1025ns ? sp73 tscr sck x input rise time (3) ?1025ns ? sp30 tdof sdo x data output fall time (3) ? ? ? ns see do32 sp31 tdor sdo x data output rise time (3) ? ? ? ns see do31 sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ??30ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? sp50 tssl2sch, tssl2scl ss x to sck x or sck x input 120 ? ? ns ? sp51 tssh2doz ss x to sdo x output high impedance (3) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ss x after sck edge 1.5 t cy +40 ??ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwis e stated. parameters are for design guidance only and are not tested. 3: assumes 50 pf load on all spi pins. ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp40 sp41 sp30,sp31 sp51 sp35 sdi x msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 20-3 for load conditions. ? 2010 microchip technology inc. ds70139g-page 175 dspic30f2011/2012/3012/3013 figure 20-15: spi module slave mode (cke = 1 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp60 sdi x sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp71 sp70 sp40 sp41 note: refer to figure 20-3 for load conditions. dspic30f2011/2012/3012/3013 ds70139g-page 176 ? 2010 microchip technology inc. table 20-32: spi module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 ts c l sck x input low time 30 ? ? ns ? sp71 tsch sck x input high time 30 ? ? ns ? sp72 tscf sck x input fall time (3) ?1025ns ? sp73 tscr sck x input rise time (3) ?1025ns ? sp30 tdof sdo x data output fall time (3) ? ? ? ns see parameter do32 sp31 tdor sdo x data output rise time (3) ? ? ? ns see parameter do31 sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ? ? ns ? sp50 tssl2sch, tssl2scl ss x to sck x or sck x input 120 ? ? ns ? sp51 tssh2doz ss to sdo x output high impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ss x after sck x edge 1.5 t cy + 40 ? ? ns ? sp60 tssl2dov sdo x data output valid after sck x edge ? ? 50 ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless other wise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. ? 2010 microchip technology inc. ds70139g-page 177 dspic30f2011/2012/3012/3013 figure 20-16: i 2 c? bus start/stop bits timing characteristics (master mode) figure 20-17: i 2 c? bus data timing characteristics (master mode) im31 im34 scl sda start condition stop condition im30 im33 note: refer to figure 20-3 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 scl sda in sda out note: refer to figure 20-3 for load conditions. dspic30f2011/2012/3012/3013 ds70139g-page 178 ? 2010 microchip technology inc. i table 20-33: i 2 c? bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im20 t f : scl sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns 400 khz mode 100 ? ns 1 mhz mode (2) ? ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 1 mhz mode (2) ? ? ns im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) ? s 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 1) ? ns hold time 400 khz mode t cy /2 (brg + 1) ? ns 1 mhz mode (2) t cy /2 (brg + 1) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (2) ??ns im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) ?? s im50 c b bus capacitive loading ? 400 pf note 1: brg is the value of the i 2 c baud rate generator. refer to section 21. ?inter-integrated circuit? (i 2 c)? (ds70068) in the dspic30f family reference manual (ds70046) . 2: maximum pin capacitance = 10 pf for all i 2 c? pins (for 1 mhz mode only). ? 2010 microchip technology inc. ds70139g-page 179 dspic30f2011/2012/3012/3013 figure 20-18: i 2 c? bus start/stop bits timing ch aracteristics (slave mode) figure 20-19: i 2 c? bus data timing characteristics (slave mode) table 20-34: i 2 c? bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz. 1 mhz mode (1) 0.5 ? s is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s is20 t f : scl sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?100ns is21 t r : scl sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?300ns note 1: maximum pin capacitance = 10 pf for all i 2 c? pins (for 1 mhz mode only). is31 is34 scl sda start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 scl sda in sda out dspic30f2011/2012/3012/3013 ds70139g-page 180 ? 2010 microchip technology inc. is25 t su : dat data input setup time 100 khz mode 250 ? ns 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 1 mhz mode (1) 0.6 ? s is34 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode (1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf table 20-34: i 2 c? bus data timing requirements (slave mode) (continued) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min max units conditions note 1: maximum pin capacitance = 10 pf for all i 2 c? pins (for 1 mhz mode only). ? 2010 microchip technology inc. ds70139g-page 181 dspic30f2011/2012/3012/3013 figure 20-20: can module i/o timing characteristics table 20-35: can module i/o timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ? 10 25 ns ca11 tior port output rise time ? 10 25 ns ca20 tcwf pulse width to trigger can wake-up filter 500 ? ? ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. c x t x pin (output) ca10 ca11 old value new value ca20 c x r x pin (input) dspic30f2011/2012/3012/3013 ds70139g-page 182 ? 2010 microchip technology inc. table 20-36: 12-bit adc module specifications ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd - 0.3 or 2.7 ? lesser of v dd + 0.3 or 5.5 v ad02 av ss module v ss supply v ss - 0.3 ? v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 2.7 ? av dd v ad06 v refl reference voltage low av ss ?av dd - 2.7 v ad07 v ref absolute reference voltage av ss - 0.3 ? av dd + 0.3 v ad08 i ref current drain ? 200 .001 300 2 a a a/d operating a/d off analog input ad10 v inh -v inl full-scale input span v refl ?v refh v see note 1 ad11 v in absolute input voltage av ss - 0.3 ? av dd + 0.3 v ? ad12 ? leakage current ? 0.001 0.610 av inl = av ss = v refl = 0v, av dd = v refh = 5v source impedance = 2.5 k ad13 ? leakage current ? 0.001 0.610 av inl = av ss = v refl = 0v, av dd = v refh = 3v source impedance = 2.5 k ad15 r ss switch resistance ? 3.2k ? ad16 c sample sample capacitor ? 18 pf ad17 r in recommended impedance of analog voltage source ? ? 2.5k dc accuracy (2) ad20 nr resolution 12 data bits bits ad21 inl integral nonlinearity ? ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad21a inl integral nonlinearity ? ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad22 dnl differential nonlinearity ? ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad22a dnl differential nonlinearity ? ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad23 g err gain error +1.25 +1.5 +3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad23a g err gain error +1.25 +1.5 +3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v note 1: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: measurements taken with external v ref + and v ref - used as the adc voltage references. ? 2010 microchip technology inc. ds70139g-page 183 dspic30f2011/2012/3012/3013 ad24 e off offset error -2 -1.5 -1.25 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad24a e off offset error -2 -1.5 -1.25 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad25 ? monotonicity (1) ? ? ? ? guaranteed dynamic performance ad30 thd total harmonic distortion ? -71 ? db ad31 sinad signal to noise and distortion ?68? db ad32 sfdr spurious free dynamic range ?83? db ad33 f nyq input signal bandwidth ? ? 100 khz ad34 enob effective number of bits 10.95 11.1 ? bits table 20-36: 12-bit adc module specifications (continued) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions note 1: the a/d conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: measurements taken with external v ref + and v ref - used as the adc voltage references. dspic30f2011/2012/3012/3013 ds70139g-page 184 ? 2010 microchip technology inc. figure 20-21: 12-bit a/d conversion timing characteristics (asam = 0 , ssrc = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ch0_samp ad60 done adif adres( 0 ) 1 2 3 4 5 6 8 7 1 - software sets adcon. samp to start sampling. 2 - sampling starts after discharge period. 3 - software clears adcon. samp to start conversion. 4 - sampling ends, conversion sequence starts. 5 - convert bit 11. 9 - one t ad for end of conversion. ad50 eoc 9 6 - convert bit 10. 7 - convert bit 1. 8 - convert bit 0. execution t samp is described in section 18. ?12-bit a/d converter? in the dspic30f family reference manual (ds70046). ? 2010 microchip technology inc. ds70139g-page 185 dspic30f2011/2012/3012/3013 table 20-37: 12-bit a/d conver sion timing requirements ac characteristics standard operating conditions: 2.7v to 5.5v (unless otherwise stated) operating temperature-40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad a/d clock period 334 ? ? ns v dd = 3-5.5v (note 1) ad51 t rc a/d internal rc oscillator period 1.2 1.5 1.8 s conversion rate ad55 t conv conversion time ? 14 t ad ns ad56a f cnv throughput rate ? 200 ? ksps v dd = v ref = 5v, industrial temperature ad56b f cnv throughput rate ? 100 ? ksps v dd = v ref = 5v, extended temperature ad57 t samp sampling time 1 t ad ?? nsv dd = 3-5.5v source resistance r s = 0-2.5 k timing parameters ad60 t pcs conversion start from sample trigger ?1 t ad ?ns ad61 t pss sample start from setting sample (samp) bit 0.5 t ad ?1.5 t ad ns ad62 t css conversion completion to sample start (asam = 1 ) ? 0.5 t ad ?ns ad63 t dpu (2) time to stabilize analog stage from a/d off to a/d on ??20 s note 1: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 2: t dpu is the time required for the adc module to stabilize when it is turned on (adcon1 dspic30f2011/2012/3012/3013 ds70139g-page 186 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 187 dspic30f2011/2012/3012/3013 21.0 packaging information 21.1 package marking information xxxxxxxxxxxxxxxxx yywwnnn 28-lead spdip example xxxxxxxxxxxxxxxxx 18-lead pdip example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn dspic30f3012 0610017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e dspic30f2012 0610017 30i/sp 3 e 30i/p 3 e 18-lead soic example yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx 0610017 30i/so dspic30f2011 3 e dspic30f2011/2012/3012/3013 ds70139g-page 188 ? 2010 microchip technology inc. 21.2 package marking information (continued) 30f2011 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic30f3013 0610017 xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn 44-lead qfn dspic 30f3013 0610017 30i/so 3 e 30i/ml 3 e 28-lead qfn-s xxxxxxx xxxxxxx yywwnnn example 30i/mm 0610017 example 3 e ? 2010 microchip technology inc. ds70139g-page 189 dspic30f2011/2012/3012/3013 !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - - ## 4 >#& . < : 9& << & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - note 1 n e1 d 1 23 a a1 a2 l e eb c e b1 b * ,1 dspic30f2011/2012/3012/3013 ds70139g-page 190 ? 2010 microchip technology inc. ! " !" #$ %&' !"( !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ? ## 4 4!! = = & # %%+ = - : >#& . -1, ## 4 >#& . 1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b note 1 d n e e1 e b 1 23 a a1 a2 l l1 h h c * , 1 ? 2010 microchip technology inc. ds70139g-page 191 dspic30f2011/2012/3012/3013 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging dspic30f2011/2012/3012/3013 ds70139g-page 192 ? 2010 microchip technology inc. ) !* ! ! !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - -- ## 4 >#& . < : 9& - -? & & 9 - 9 # 4!! < 6 9 #>#& ) 9 * 9 #>#& ) < : * + 1 = = - note 1 n 12 d e1 eb c e l a2 e b b1 a1 a 3 * ,1 ? 2010 microchip technology inc. ds70139g-page 193 dspic30f2011/2012/3012/3013 ) ! " !" #$ %&' !"( !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ? ## 4 4!! = = & # %%+ = - : >#& . -1, ## 4 >#& . 1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n * , 1 dspic30f2011/2012/3012/3013 ds70139g-page 194 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2010 microchip technology inc. ds70139g-page 195 dspic30f2011/2012/3012/3013 ) + , $ *- .. /0/0&1 +, ! 2 3 &4 ( - 3 !" #$% &" ' ()"&'"!&) &#*& & & # 4 !! *!" &# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & < & # %% , & & 4!! - .3 : >#& . ?1, .$ !# #>#& . -? - : 9& ?1, .$ !# #9& -? - , & &>#& ) - -< - , & &9& 9 - , & && .$ !# # c = = d e 2 1 n e2 exposed pad 2 1 d2 n e b k l note 1 a3 a a1 top view bottom view * , 1 dspic30f2011/2012/3012/3013 ds70139g-page 196 ? 2010 microchip technology inc. ) + , $ *- .. /0/0&1 +, ! 2 3 &4 ( - 3 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2010 microchip technology inc. ds70139g-page 197 dspic30f2011/2012/3012/3013 44 + , $ *- . 0 +, !" #$% &" ' ()"&'"!&) &#*& & & # 4 !! *!" &# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 & ? 1, : 8 & < & # %% , & & 4!! - .3 : >#& . <1, .$ !# #>#& . ?- ? ?< : 9& <1, .$ !# #9& ?- ? ?< , & &>#& ) - -< , & &9& 9 - , & && .$ !# # c = = d exposed pad d2 e b k l e2 2 1 n note 1 2 1 e n bottom view top view a3 a1 a * , -1 dspic30f2011/2012/3012/3013 ds70139g-page 198 ? 2010 microchip technology inc. 44 + , $ *- . 0 +, 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2010 microchip technology inc. ds70139g-page 199 dspic30f2011/2012/3012/3013 appendix a: revision history revision d (august 2006) previous versions of this data sheet contained advance or preliminary information. they were distributed with incomplete characterization data. this revision reflects these updates: ? supported i 2 c slave addresses (see table 14-1 ) ? adc conversion clock selection to allow 200 khz sampling rate (see section 16.0 ?12-bit analog-to-digital conv erter (adc) module? ) ? operating current (i dd ) specifications (see table 20-5 ) ? idle current (i idle ) specifications (see table 20-6 ) ? power-down current (i pd ) specifications (see table 20-7 ) ? i/o pin input specifications (see table 20-8 ) ? bor voltage limits (see table 20-11 ) ? watchdog timer time-out limits (see table 20-21 ) revision e (december 2006) this revision includes updates to the packaging diagrams. revision f (may 2008) this revision reflects these updates: ? added fuse configuration register (ficd) details (see section 17.7 ?device configuration registers? and table 17-8 ) ? added note 2 to device configuration registers table ( table 17-8 ) ? updated bit 10 in the uart2 register map (see table 15-2 ). this bit is unimplemented. ? electrical specifications: - resolved tbd values for parameters do10, do16, do20, and do26 (see ta b l e 2 0 - 9 ) - 10-bit high-speed adc t pdu timing parameter (time to stabilize) has been updated from 20 s typical to 20 s maximum (see table 20-37 ) - parameter os65 (internal rc accuracy) has been expanded to reflect multiple min and max values for different temperatures (see table 20-19 ) - parameter dc12 (ram data retention voltage) has been updated to include a min value (see table 20-4 ) - parameter d134 (erase/write cycle time) has been updated to include min and max values and the typ value has been removed (see table 20-12 ) - removed parameters os62 (internal frc jitter) and os64 (internal frc drift) and note 2 from ac characteristics (see table 20-18 ) - parameter os63 (internal frc accuracy) has been expanded to reflect multiple min and max values for different temperatures (see table 20-18 ) - updated min and max values and conditions for parameter sy11 and updated min, typ, and max values and conditions for parameter sy20 (see table 20-21 ) ? additional minor corrections throughout the document dspic30f2011/2012/3012/3013 ds70139g-page 200 ? 2010 microchip technology inc. revision g (november 2010) this revision includes minor typographical and formatting changes throughout the data sheet text. the major changes are referenced by their respective section in ta b l e a - 1 . table a-1: major section updates section name update description ? high-performance, 16-bit digital signal controllers ? added note 1 to all qfn pin diagrams (see ? pin diagrams ? ). section 1.0 ?device overview? updated the pinout i/o descriptions for av dd and av ss (see ta b l e 1 - 1 ). section 17.0 ?system integration? added a shaded note on osctun functionality in section 17.2.5 ?fast rc oscillator (frc)? . section 20.0 ?electrical characteristics? updated the maximum value for parameter di19 and the minimum value for parameter di29 in the i/o pin input specifications (see ta b l e 2 0 - 8 ). removed parameter d136 and updated the minimum, typical, maximum, and conditions for parameters d122 and d134 in the program and eeprom specifications (see table 20-12 ). renamed parameter ad56 to ad56a and added parameter ad56b to the 12-bit a/d conversion timing requirements (see ta b l e 2 0 - 3 7 ). ? product identifi cation system ? added the ?mm? package definition. ? 2010 microchip technology inc. ds70139g-page 201 dspic30f2011/2012/3012/3013 index numerics 12-bit analog-to-digital converter (a/d) module .............. 113 a a/d .................................................................................... 113 aborting a conversion .............................................. 115 adchs register ....................................................... 113 adcon1 register..................................................... 113 adcon2 register..................................................... 113 adcon3 register..................................................... 113 adcssl register ..................................................... 113 adpcfg register..................................................... 113 configuring analog port pins.............................. 60, 119 connection considerations....................................... 119 conversion operation ............................................... 114 effects of a reset...................................................... 118 operation during cpu idle mode ............................. 118 operation during cpu sleep mode.......................... 118 output formats ......................................................... 118 power-down modes.................................................. 118 programming the sample trigger............................. 115 register map............................................................. 121 result buffer ............................................................. 114 sampling requirements............................................ 117 selecting the conversion sequence......................... 114 ac characteristics ............................................................ 160 load conditions ........................................................ 160 ac temperature and voltage specifications .................... 160 adc selecting the conversion clock ................................ 115 adc conversion speeds .................................................. 116 address generator units .................................................... 43 alternate vector table ........................................................ 69 analog-to-digital converter. see adc. assembler mpasm assembler................................................... 146 automatic clock stretch.................................................... 100 during 10-bit addressing (stren = 1)..................... 100 during 7-bit addressing (stren = 1)....................... 100 receive mode ........................................................... 100 transmit mode .......................................................... 100 b bandgap start-up time requirements............................................................ 166 timing characteristics .............................................. 166 barrel shifter ....................................................................... 27 bit-reversed addressing .................................................... 46 example ...................................................................... 47 implementation ........................................................... 46 modifier values table ................................................. 47 sequence table (16-entry)......................................... 47 block diagrams 12-bit adc functional............................................... 113 16-bit timer1 module .................................................. 73 16-bit timer2............................................................... 79 16-bit timer3............................................................... 79 32-bit timer2/3............................................................ 78 dsp engine ................................................................ 24 dspic30f2011 ............................................................ 12 dspic30f2012 ............................................................ 13 dspic30f3013 ............................................................ 15 external power-on re set circuit............................... 131 i 2 c .............................................................................. 98 input capture mode.................................................... 83 oscillator system...................................................... 125 output compare mode ............................................... 87 reset system ........................................................... 129 shared port structure................................................. 59 spi.............................................................................. 94 spi master/slave connection..................................... 95 uart receiver......................................................... 106 uart transmitter..................................................... 105 bor characteristics ......................................................... 158 bor. see brown-out reset. brown-out reset characteristics.......................................................... 158 timing requirements ............................................... 165 c c compilers mplab c18.............................................................. 146 can module i/o timing characteristics ........................................ 181 i/o timing requirements.......................................... 181 clkout and i/o timing characteristics.......................................................... 164 requirements ........................................................... 164 code examples data eeprom block erase ....................................... 56 data eeprom block write ........................................ 58 data eeprom read.................................................. 55 data eeprom word erase ....................................... 56 data eeprom word write ........................................ 57 erasing a row of program memory ........................... 51 initiating a programming sequence ........................... 52 loading write latches................................................ 52 code protection ................................................................ 123 control registers ................................................................ 50 nvmadr .................................................................... 50 nvmadru ................................................................. 50 nvmcon.................................................................... 50 nvmkey .................................................................... 50 core architecture overview..................................................................... 19 cpu architecture overview ................................................ 19 customer change notification service............................. 205 customer notification service .......................................... 205 customer support............................................................. 205 d data accumulators and adder/subtractor .......................... 25 data space write saturation ...................................... 27 overflow and saturation ............................................. 25 round logic ............................................................... 26 write-back .................................................................. 26 data address space........................................................... 35 alignment.................................................................... 38 alignment (figure) ...................................................... 38 effect of invalid memory accesses (table) ................ 38 mcu and dsp (mac class) instructions example .... 37 memory map......................................................... 35, 36 near data space ........................................................ 39 software stack ........................................................... 39 spaces........................................................................ 38 width .......................................................................... 38 data eeprom memory...................................................... 55 erasing ....................................................................... 56 erasing, block............................................................. 56 dspic30f2011/2012/3012/3013 ds70139g-page 202 ? 2010 microchip technology inc. erasing, word ............................................................. 56 protection against spurious write .............................. 58 reading....................................................................... 55 write verify ................................................................. 58 writing ......................................................................... 57 writing, block .............................................................. 57 writing, word .............................................................. 57 dc characteristics ............................................................ 150 bor .......................................................................... 158 brown-out reset ....................................................... 158 i/o pin input specifications ....................................... 156 i/o pin output specifications .................................... 156 idle current (i idle ) .................................................... 153 low-voltage detect................................................... 157 lvdl ......................................................................... 157 operating current (i dd )............................................. 152 power-down current (i pd ) ........................................ 154 program and eeprom............................................. 159 temperature and voltage specifications .................. 150 development support ....................................................... 145 device configuration register map............................................................. 136 device configuration registers fborpor ................................................................ 134 fgs........................................................................... 134 fosc ........................................................................ 134 fwdt........................................................................ 134 device overview ........................................................... 11, 19 disabling the uart........................................................... 107 divide support..................................................................... 22 instructions (table) ..................................................... 22 dsp engine......................................................................... 23 multiplier...................................................................... 25 dual output compare match mode .................................... 88 continuous pulse mode .............................................. 88 single pulse mode ...................................................... 88 e electrical characteristics ac ............................................................................. 160 dc ............................................................................. 150 enabling and setting up uart alternate i/o .............................................................. 107 setting up data, parity and stop bit selections ....... 107 enabling the uart ........................................................... 107 equations adc conversion clock ............................................. 115 baud rate ................................................................. 109 serial clock rate ...................................................... 102 errata .................................................................................... 9 exception sequence trap sources .............................................................. 67 external clock timi ng characteristics type a, b and c timer ............................................. 167 external clock timing requirements................................ 161 type a timer ............................................................ 167 type b timer ............................................................ 168 type c timer ............................................................ 168 external interrupt requests ................................................ 70 f fast context saving............................................................ 70 flash program memory....................................................... 49 i i/o pin specifications input.......................................................................... 156 output ....................................................................... 156 i/o ports.............................................................................. 59 parallel (pio) .............................................................. 59 i 2 c 10-bit slave mode operation........................................ 99 reception ................................................................. 100 transmission ............................................................ 100 i 2 c 7-bit slave mode operation.......................................... 99 reception ................................................................... 99 transmission .............................................................. 99 i 2 c master mode operation.............................................. 101 baud rate generator ............................................... 102 clock arbitration ....................................................... 102 multi-master communication, bus collision and bus arbitration ..................... 102 reception ................................................................. 102 transmission ............................................................ 101 i 2 c master mode support ................................................. 101 i 2 c module addresses................................................................... 99 bus data timing characteristics master mode..................................................... 177 slave mode....................................................... 179 bus data timing requirements master mode..................................................... 178 slave mode....................................................... 179 bus start/stop bits timing characteristics master mode..................................................... 177 slave mode....................................................... 179 general call address support .................................. 101 interrupts .................................................................. 101 ipmi support............................................................. 101 operating function description .................................. 97 operation during cpu sleep and idle modes .......... 102 pin configuration ........................................................ 97 programmer?s model .................................................. 97 register map ............................................................ 103 registers .................................................................... 97 slope control ............................................................ 101 software controlled clock stretching (stren = 1) . 100 various modes............................................................ 97 idle current (i idle ) ............................................................ 153 in-circuit serial programming (icsp)......................... 49, 123 input capture (capx) timing characteristics .................. 169 input capture module ......................................................... 83 interrupts .................................................................... 84 register map .............................................................. 85 input capture operation during sleep and idle modes...... 84 cpu idle mode ........................................................... 84 cpu sleep mode ........................................................ 84 input capture timing requirements................................. 169 input change notification module....................................... 63 dspic30f2012/3013 register map (bits 7-0)............. 63 instruction addressing modes ............................................ 43 file register instructions ............................................ 43 fundamental modes supported ................................. 43 mac instructions ........................................................ 44 mcu instructions ........................................................ 43 move and accumulator instructions............................ 44 other instructions ....................................................... 44 instruction set overview................................................................... 140 summary .................................................................. 137 internal clock timing examples ....................................... 163 internet address ............................................................... 205 ? 2010 microchip technology inc. ds70139g-page 203 dspic30f2011/2012/3012/3013 interrupt controller register map......................................................... 71, 72 interrupt priority .................................................................. 66 traps........................................................................... 67 interrupt sequence ............................................................. 69 interrupt stack frame ................................................. 69 interrupts ............................................................................. 65 l load conditions ................................................................ 160 low voltage detect (lvd) ................................................ 133 low-voltage detect characteristics .................................. 157 lvdl characteristics ........................................................ 157 m memory organization.......................................................... 29 core register map...................................................... 39 microchip internet web site .............................................. 205 modulo addressing ............................................................. 44 applicability ................................................................. 46 incrementing buffer operation example..................... 45 start and end address................................................ 45 w address register selection .................................... 45 mplab asm30 assembler, linker, librarian ................... 146 mplab integrated development environment software .. 145 mplab pm3 device programmer .................................... 148 mplab real ice in-circuit emulator system................. 147 mplink object linker/mplib object librarian ................ 146 n nvm register map............................................................... 53 o oc/pwm module timing characteristics.......................... 171 operating current (i dd )..................................................... 152 operating frequency vs voltage dspic30fxxxx-20 (extended)................................. 150 oscillator configurations........................................................... 126 fail-safe clock monitor .................................... 128 fast rc (frc) .................................................. 127 initial clock source selection ........................... 126 low-power rc (lprc)..................................... 127 lp oscillator control ......................................... 127 phase locked loop (pll) ................................ 127 start-up timer (ost) ........................................ 126 operating modes (table) .......................................... 124 system overview ...................................................... 123 oscillator selection ........................................................... 123 oscillator start-up timer timing characteristics .............................................. 165 timing requirements................................................ 165 output compare interrupts ................................................. 90 output compare module..................................................... 87 register map............................................................... 91 timing characteristics .............................................. 170 timing requirements................................................ 170 output compare operation during cpu idle mode............ 90 output compare sleep mode operation ............................ 90 p packaging information ...................................................... 187 marking ............................................................. 187, 188 peripheral module disable (pmd) registers .................... 135 pinout descriptions ............................................................. 16 pll clock timing spec ifications ...................................... 162 por. see power-on reset. port write/read example ................................................... 60 portb register map for dspic30f2011/3012 ....................... 61 register map for dspic30f2012/3013 ....................... 61 portc register map for dspic30f2011/2012/3012/3013 ..... 61 portd register map for dspic30f2011/3012 ....................... 61 register map for dspic30f2012/3013 ....................... 62 portf register map for dspic30f2012/3013 ....................... 62 power saving modes........................................................ 133 idle............................................................................ 134 sleep ........................................................................ 133 sleep and idle........................................................... 123 power-down current (i pd )................................................ 154 power-up timer timing characteristics .............................................. 165 timing requirements ............................................... 165 program address space..................................................... 29 construction ............................................................... 31 data access from program memory using program space visibility..................................... 33 data access from program memory using table instructions ............................................... 32 data access from, address generation ..................... 31 data space window into operation ........................... 34 data table access (ls word) .................................... 32 data table access (ms byte) .................................... 33 memory maps............................................................. 30 table instructions tblrdh ............................................................. 32 tblrdl.............................................................. 32 tblwth............................................................. 32 tblwtl ............................................................. 32 program and eeprom characteristics............................ 159 program counter ................................................................ 20 programmable .................................................................. 123 programmer?s model .......................................................... 20 diagram ...................................................................... 21 programming operations.................................................... 51 algorithm for program flash....................................... 51 erasing a row of program memory ........................... 51 initiating the programming sequence ........................ 52 loading write latches................................................ 52 protection against accidental writes to osccon ........... 128 r reader response............................................................. 206 reset ........................................................................ 123, 129 bor, programmable ................................................ 131 brown-out reset (bor)............................................ 123 oscillator start-up timer (ost)................................ 123 por operating without fscm and pwrt................ 131 with long crystal start-up time ...................... 131 por (power-on reset)............................................. 129 power-on reset (por)............................................. 123 power-up timer (pwrt) .......................................... 123 reset sequence ................................................................. 67 reset sources ............................................................ 67 reset sources brown-out reset (bor).............................................. 67 illegal instruction trap ................................................ 67 dspic30f2011/2012/3012/3013 ds70139g-page 204 ? 2010 microchip technology inc. trap lockout ............................................................... 67 uninitialized w register trap ..................................... 67 watchdog time-out..................................................... 67 reset timing characteristics ............................................ 165 reset timing requirements.............................................. 165 run-time self-programming (rtsp) ................................. 49 s simple capture event mode ............................................... 83 buffer operation.......................................................... 84 hall sensor mode ....................................................... 84 prescaler ..................................................................... 83 timer2 and timer3 selection mode ............................ 84 simple oc/pwm mode timing requirements.................. 171 simple output compare match mode................................. 88 simple pwm mode ............................................................. 88 input pin fault protection............................................ 88 period.......................................................................... 89 software simulator (mplab sim)..................................... 147 software stack pointer, frame pointer............................... 20 call stack frame...................................................... 39 spi module.......................................................................... 93 framed spi support ................................................... 94 operating function description .................................. 93 operation during cpu idle mode ............................... 95 operation during cpu sleep mode ............................ 95 sdox disable ............................................................. 94 slave select synchronization ..................................... 95 spi1 register map ...................................................... 96 timing characteristics master mode (cke = 0) .................................... 172 master mode (cke = 1) .................................... 173 slave mode (cke = 1) .............................. 174, 175 timing requirements master mode (cke = 0) .................................... 172 master mode (cke = 1) .................................... 173 slave mode (cke = 0) ...................................... 174 slave mode (cke = 1) ...................................... 176 word and byte communication .................................. 94 status bits, their significance and the initialization condition for rcon register, case 1............................................ 132 status bits, their significance and the initialization condition for rcon register, case 2 ...................................... 132 status register.................................................................... 20 symbols used in opcode descriptions............................. 138 system integration register map............................................................. 136 t table instruction operation summary ................................ 49 temperature and voltage specifications ac ............................................................................. 160 dc ............................................................................. 150 timer 2/3 module ................................................................ 77 timer1 module .................................................................... 73 16-bit asynchronous counter mode ........................... 73 16-bit synchronous counter mode ............................. 73 16-bit timer mode ....................................................... 73 gate operation ........................................................... 74 interrupt....................................................................... 74 operation during sleep mode .................................... 74 prescaler ..................................................................... 74 real-time clock ......................................................... 74 interrupts............................................................. 74 oscillator operation ............................................ 74 register map .............................................................. 75 timer2 and timer3 selection mode.................................... 88 timer2/3 module 16-bit timer mode....................................................... 77 32-bit synchronous counter mode ............................. 77 32-bit timer mode....................................................... 77 adc event trigger...................................................... 80 gate operation ........................................................... 80 interrupt ...................................................................... 80 operation during sleep mode .................................... 80 register map .............................................................. 81 timer prescaler .......................................................... 80 timing characteristics a/d conversion low-speed (asam = 0, ssrc = 000) .............. 184 bandgap start-up time............................................. 166 can module i/o........................................................ 181 clkout and i/o ...................................................... 164 external clock........................................................... 160 i 2 c bus data master mode..................................................... 177 slave mode....................................................... 179 i 2 c bus start/stop bits master mode..................................................... 177 slave mode....................................................... 179 input capture (capx)............................................... 169 oc/pwm module...................................................... 171 oscillator start-up timer........................................... 165 output compare module .......................................... 170 power-up timer ........................................................ 165 reset ........................................................................ 165 spi module master mode (cke = 0).................................... 172 master mode (cke = 1).................................... 173 slave mode (cke = 0)...................................... 174 slave mode (cke = 1)...................................... 175 type a, b and c timer external clock ..................... 167 watchdog timer ....................................................... 165 timing diagrams pwm output timing ................................................... 89 time-out sequence on power-up (mclr not tied to v dd ), case 1 ..................... 130 time-out sequence on power-up (mclr not tied to v dd ), case 2.................................. 130 time-out sequence on power-up (mclr tied to v dd )...................................................... 130 timing diagrams and specifications dc characteristics - internal rc accuracy............... 163 timing diagrams.see timing characteristics timing requirements a/d conversion low-speed ........................................................ 185 bandgap start-up time............................................. 166 brown-out reset ....................................................... 165 can module i/o........................................................ 181 clkout and i/o ...................................................... 164 external clock........................................................... 161 i 2 c bus data (master mode) .................................... 178 i 2 c bus data (slave mode) ...................................... 179 input capture ............................................................ 169 oscillator start-up timer........................................... 165 output compare module .......................................... 170 power-up timer ........................................................ 165 ? 2010 microchip technology inc. ds70139g-page 205 dspic30f2011/2012/3012/3013 reset......................................................................... 165 simple oc/pwm mode............................................. 171 spi module master mode (cke = 0) .................................... 172 master mode (cke = 1) .................................... 173 slave mode (cke = 0) ...................................... 174 slave mode (cke = 1) ...................................... 176 type a timer external clock .................................... 167 type b timer external clock .................................... 168 type c timer external clock .................................... 168 watchdog timer........................................................ 165 timing specifications pll clock.................................................................. 162 trap vectors ....................................................................... 69 u uart module address detect mode ............................................... 109 auto-baud support ................................................... 109 baud rate generator................................................ 109 enabling and setting up ........................................... 107 framing error (ferr)............................................... 109 idle status ................................................................. 109 loopback mode ........................................................ 109 operation during cpu sleep and idle modes .......... 110 overview ................................................................... 105 parity error (perr) .................................................. 109 receive break........................................................... 109 receive buffer (uxrxb) ........................................... 108 receive buffer overrun error (oerr bit) ................ 108 receive interrupt....................................................... 108 receiving data.......................................................... 108 receiving in 8-bit or 9-bit data mode........................ 108 reception error handling.......................................... 108 transmit break.......................................................... 108 transmit buffer (uxtxb)........................................... 107 transmit interrupt...................................................... 108 transmitting data...................................................... 107 transmitting in 8-bit data mode................................ 107 transmitting in 9-bit data mode................................ 107 uart1 register map................................................ 111 uart2 register map................................................ 111 uart operation idle mode .................................................................. 110 sleep mode............................................................... 110 unit id locations............................................................... 123 universal asynchronous receiver transmitter (uart) module ......................................................... 105 w wake-up from sleep ......................................................... 123 wake-up from sleep and idle ............................................. 70 watchdog timer timing characteristics .............................................. 165 timing requirements................................................ 165 watchdog timer (wdt) ............................................ 123, 133 enabling and disabling ............................................. 133 operation .................................................................. 133 www address.................................................................. 205 www, on-line support ....................................................... 9 dspic30f2011/2012/3012/3013 ds70139g-page 206 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds70139g-page 207 dspic30f2011/2012/3012/3013 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com dspic30f2011/2012/3012/3013 ds70139g-page 208 ? 2010 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70139g dspic30f2011/2012/3012/3013 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2010 microchip technology inc. ds70139g-page 209 dspic30f2011/2012/3012/3013 product identification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. dspic30f3013at-30i/sp-es example: dspic30f3013at-30i/sp = 30 mips, industr ial temp., spdip package, rev. a trademark architecture flash e = extended high temp -40c to +125c i = industrial -40c to +85c temperature device id package p=dip so = soic sp = spdip ml = qfn (8x8) mm = qfn-s (6x6) memory size in bytes 0 = romless 1 = 1k to 6k 2 = 7k to 12k 3 = 13k to 24k 4 = 25k to 48k 5 = 49k to 96k 6 = 97k to 192k 7 = 193k to 384k 8 = 385k to 768k 9 = 769k and up custom id (3 digits) or t = tape and reel a,b,c? = revision level engineering sample (es) speed 20 = 20 mips 30 = 30 mips ds70139g-page 210 ? 2010 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 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